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Author SHA1 Message Date
Marcelina Kościelnicka 1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message. 
This is a fixed version of #3072.
 2021-12-09 00:56:14 +01:00
Pepijn de Vos 0c7461fe5e
gowin: widelut support (#3042) 2021-11-06 16:09:30 +01:00
Marcelina Kościelnicka 4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka 63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load. 
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka 9cbff3a4a9 opt_merge: Remove and reinsert init when connecting nets. 
Mutating the SigMap by adding a new connection will throw off FfInitVals
index.  Work around this by removing the relevant init values from index
whenever we connect nets, then re-add the new init value.

Should fix #2920.
 2021-08-22 18:34:11 +02:00
Marcelina Kościelnicka 62d41d4639 opt_clean: Make the init attribute follow the FF's Q. 
Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire.  This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.

Part of another jab at #2920.
 2021-08-22 15:38:29 +02:00
Marcelina Kościelnicka f791328506 Add opt_mem_widen pass. 
If all of us are wide, then none of us are!
 2021-08-14 01:06:23 +02:00
Marcelina Kościelnicka 616ace2d92 Add new opt_mem_priority pass. 2021-08-13 11:58:52 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka e6f3d1c225 kernel/mem: Introduce transparency masks. 2021-08-11 00:04:16 +02:00
Marcelina Kościelnicka d25b9088c8 Refactor common parts of SAT-using optimizations into a helper. 
This also aligns the functionality:

- in all cases, the onehot attribute is used to create appropriate
  constraints (previously, opt_dff didn't do it at all, and share
  created one-hot constraints based on $pmux presence alone, which
  is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
  importing the SAT problem (previously only memory_share did this)
  — this avoids creating clauses for hard cells that are unlikely
  to help with proving the UNSATness needed for optimization
 2021-08-09 16:54:35 +02:00
Marcelina Kościelnicka 98003430d6 opt_merge: Use FfInitVals. 
Partial #2920 fix.
 2021-08-08 01:19:22 +02:00
Marcelina Kościelnicka 54e75129e5 opt_lut: Allow more than one -dlogic per cell type. 
Fixes #2061.
 2021-07-29 17:30:07 +02:00
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka 436d42c00c opt_expr: Propagate constants to port connections. 
This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value.  This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
 2021-07-27 20:44:26 +02:00
gatecat 6a6d049f1c opt_muxtree: Update port_off and port_idx even for constant bits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-11 12:06:35 +01:00
Marcelina Kościelnicka 1667ad658b opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits. 
The previous code, in addition to being needlessly limitted to 32 bits
in the first place, also had UB for the 31th bit (doing 1 << 31).
 2021-06-09 19:53:44 +02:00
Marcelina Kościelnicka 12b3a9765d opt_expr: Optimize div/mod by const 1. 
Turns out the code for div by a power of 2 is already almost capable of
optimizing this to a shift-by-0 or and-with-0, which will be further
folded into nothingness; let's beef it up to handle div by 1 as well.

Fixes #2820.
 2021-06-09 17:42:30 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka 83a218141c kernel/mem: Add sub_addr helpers. 2021-05-26 03:34:02 +02:00
Marcelina Kościelnicka e6b078d156 opt_mem: Add reset/init value support. 2021-05-25 20:06:00 +02:00
Marcelina Kościelnicka 5628f5a88f opt_mem_feedback: Respect write port priority. 2021-05-25 15:59:41 +02:00
Marcelina Kościelnicka 9d5d5a48b1 opt_mem_feedback: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka 835688bf80 opt_mem_feedback: Rewrite feedback path finding logic. 
Fixes #2766.
 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka b706adb809 opt_mem_feedback: Convert to Mem helpers. 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka d905990d01 memory_share: Split off feedback path finding as a separate pass. 
memory_share is actually three passes in a trenchcoat.  Split off the
one that has the least in common with the other two as a separate pass.
 2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka a23d9409e7 opt_mem: Remove write ports with const-0 EN. 
Fixes #2765.
 2021-05-23 14:30:56 +02:00
Marcelina Kościelnicka 5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. 2021-05-04 21:03:40 +02:00
Marcelina Kościelnicka 3af871f969 opt_clean: Remove init attribute bits together with removed DFFs. 
Fixes #2546.
 2021-03-15 17:16:53 +01:00
Marcelina Kościelnicka 01626e6746 opt_share: Fix X and CO signal width for shifted $alu in opt_share. 
These need to be the same length as actual Y, not visible part of Y.

Fixes #2538.
 2021-01-14 14:54:08 +01:00
StefanBruens 9396678db4
Fix use-after-free in LUT opt pass 
RTLIL::Module::remove(Cell* cell) calls `delete cell`.

Any subsequent accesses of `cell` then causes undefined behavior.
 2020-12-22 03:23:42 +01:00
Marcelina Kościelnicka 06141db233 opt_mem: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 7670a89e1f opt_clean: Better memory handling. 
Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself).  With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
 2020-10-08 18:05:51 +02:00
N. Engelhardt 3238190797 use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
clairexen a96df40814
Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes 
opt_share: Refactor, fix some bugs.
 2020-08-20 16:24:53 +02:00
clairexen 1d0d9d5c86
Merge pull request #2337 from YosysHQ/mwk/clean-keep-wire 
opt_clean: Fix module keep rules.
 2020-08-20 16:23:55 +02:00
Marcelina Kościelnicka 2b777bbda8 opt_share: Refactor, fix some bugs. 
Fixes #2334.
Fixes #2335.
Fixes #2336.
 2020-08-17 17:26:36 +02:00
Marcelina Kościelnicka 2ab350a7b0 opt_clean: Fix module keep rules. 
- wires with keep attribute now force a module to be kept
- presence of $memwr and $meminit cells no longer forces a module to be
  kept
 2020-08-09 13:57:00 +02:00
Marcelina Kościelnicka acd8c5c205 Remove now-redundant opt_rmdff pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka 6cd135a5eb opt_expr: Remove -clkinv option, make it the default. 
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
 2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka af6623ebb8 Add opt_dff pass. 2020-07-30 18:27:04 +02:00
Marcelina Kościelnicka dc18bf1969 opt_expr: Fix handling of $_XNOR_ cells with A = B. 
Fixes #2311.
 2020-07-29 12:41:43 +02:00
Marcelina Kościelnicka 31d6107521 pmux2shift: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 4d9105ccb0 wreduce: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 61a7ec4768 opt_merge: Dedup one more use of FF cell type list. 2020-07-15 06:19:18 +02:00
Marcelina Kościelnicka 7afcb72c98 opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. 
Fixes #2221.
 2020-07-05 06:31:58 +02:00
Marcelina Kościelnicka 77b15dd8e9 opt_merge: use the master FF type list 2020-06-30 20:57:35 +02:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs 
Use (and ignore) the expression provided to log_assert in NDEBUG builds
 2020-06-25 18:21:51 +02:00
Marcelina Kościelnicka 119f79d8b9 Add support for new FF types in some opt passes. 2020-06-23 15:40:02 +02:00
whitequark 118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Claire Wolf 3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 15:54:14 +02:00
Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
Eddie Hung 7b3a4a1fff opt_expr: Sx to Sz; spotted by @Xiretza 2020-05-14 12:14:23 -07:00
Eddie Hung 73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
 2020-05-14 11:56:22 -07:00
Eddie Hung cd92a706ae Fix whitespace 2020-05-14 09:51:17 -07:00
Eddie Hung 5be4b00a0d opt_clean: improve warning message 2020-05-14 00:59:38 -07:00
Eddie Hung fc9fb09a91 opt_clean: rminit without -purge; also remove if consistent with const.. 
warn otherwise
 2020-05-14 00:31:08 -07:00
Eddie Hung 68b31f5e99 opt_clean: really make 'clean' identical to 'opt_clean' by rminit too 2020-05-14 00:31:08 -07:00
Eddie Hung 9694dc42dd opt_expr: consume_x to require/imply !keepdc 2020-05-08 11:12:43 -07:00
Eddie Hung 17f4e06247 opt_expr: restore consume_x; use for coarse grained too 2020-05-08 11:07:44 -07:00
Claire Wolf 2285cf1219 Fix the other "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 21:50:43 +02:00
Claire Wolf 8ee32adac3 Fix "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-01 20:12:16 +02:00
Eddie Hung b5f38f8342 opt_expr: const_xnor replacement to pad Y with 1'b1 2020-04-24 14:13:45 -07:00
Eddie Hung 83570bc0da opt_expr: more fixes for $xor/$xnor 2020-04-24 11:15:29 -07:00
Eddie Hung 90b71eb84b opt_expr: do not group by X, more fixes 2020-04-23 18:15:07 -07:00
Eddie Hung e7058593f4 opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too 2020-04-23 15:57:48 -07:00
Marcelina Kościelnicka 2f8541a92e opt_expr: Fix X and CO outputs for $alu identity-mapping rules. 2020-04-16 11:48:29 +02:00
Marcelina Kościelnicka 85166633bc opt_clean: Add missing assignments to opt.did_something. 2020-04-15 16:20:56 +02:00
Marcelina Kościelnicka 6c16fd760b opt_expr: Add more $alu optimizations. 
Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.

Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).

Fixes #1912.
 2020-04-14 21:48:13 +02:00
Marcelina Kościelnicka 840bb17089 opt_expr: Optimize multiplications with low 0 bits in operands. 
Fixes #1500.
 2020-04-13 16:52:22 +02:00
Marcelina Kościelnicka 516857f3ba [NFCI] Deduplicate builtin FF cell types list 
A few passes included the same list of FF cell types.  Make it a global
const instead.

The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
 2020-04-09 18:05:06 +02:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung 37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Eddie Hung c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup 
kernel: share a single CellTypes within a pass
 2020-04-01 14:17:45 -07:00
Eddie Hung 4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor 
opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
 2020-04-01 14:17:01 -07:00
Eddie Hung e79bc45975
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu 
opt_expr: improve performance on $alu and $sub
 2020-04-01 14:11:09 -07:00
Eddie Hung 4d897975a8 Code review fixes 2020-03-30 08:22:46 -07:00
Eddie Hung f64d59d824
Apply suggestions from code review 
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-03-30 08:19:56 -07:00
Eddie Hung d40f12252b kernel: clear some more ShareWorker state 2020-03-26 15:05:45 -07:00
Eddie Hung 0c0dc4ffc3 opt_expr: fix failing $xnor test 2020-03-20 14:39:08 -07:00
Eddie Hung af16ca9dd4 opt_expr: fix missing brace 2020-03-20 09:17:53 -07:00
Eddie Hung 01f9aabc2f opt_expr: extend to $xnor and $_XNOR_ 2020-03-19 16:56:39 -07:00
Eddie Hung ee5995641e opt_expr: optimise 1-bit $xor or $_XOR_ with constant input 2020-03-19 16:33:54 -07:00
Eddie Hung 8d1fa0e3b9 opt_expr: remove redundant 2020-03-19 14:34:27 -07:00
Eddie Hung 213a895589 opt_expr: optimise $sub when both A[i] and B[i] == 1'b1 2020-03-19 14:34:10 -07:00
Eddie Hung a8e5d0c402 opt_expr: optimise for identity $alu-s just like $add/$sub 2020-03-19 14:24:55 -07:00
Eddie Hung 7ad7f41bc5 kernel: share a single CellTypes within a pass 2020-03-18 12:21:40 -07:00
Eddie Hung cdf17c4455 opt_merge: unordered_map -> dict as per @cliffordwolf review 2020-03-16 12:44:33 -07:00
Eddie Hung 9f30d7f843 opt_merge: speedup 2020-03-16 12:43:54 -07:00
Eddie Hung 432a09af80 kernel: SigSpec use more const& + overloads to prevent implicit SigSpec 2020-03-13 08:17:39 -07:00
Eddie Hung de3e5fcdc6 ystests: fix write_smt2_write_smt2_cyclic_dependency_fail 2020-02-28 12:33:55 -08:00
Eddie Hung 1d401a7991 clean: ignore specify-s inside cells when determining whether to keep 2020-02-19 10:45:10 -08:00
Eddie Hung 505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init 
opt_merge: discard \init of '$' cells with 'Q' port when merging
 2020-02-05 14:56:26 -08:00
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Claire Wolf 1679682fa3 Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys 
Also some minor fixes to the original PR.
 2020-01-29 17:01:24 +01:00
Eddie Hung a855f23f22 Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init 2020-01-28 12:46:18 -08:00