The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
If an init value is emitted for a reg, an (*init*) attribute is never
necessary, since it is exactly equivalent. On the other hand, some
tools that consume Verilog (ISE, Vivado, Quartus) complain about
(*init*) attributes because their interpretation differs from Yosys.
All (*init*) attributes that would not become reg init values anyway
are emitted as before.
Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.
After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)
Fixes#948 (again).
Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
This commit fixes two related issues:
* For asynchronous ports, clock is no longer added to domain list.
(This would lead to absurd constructs like `always @(posedge 0)`.
* The logic to distinguish synchronous and asynchronous ports is
changed to correctly use or avoid clock in all cases.
Before this commit, the following RTLIL snippet (after memory_collect)
cell $memrd $2
parameter \MEMID "\\mem"
parameter \ABITS 2
parameter \WIDTH 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 1
parameter \TRANSPARENT 1
connect \CLK 1'0
connect \EN 1'1
connect \ADDR \mem_r_addr
connect \DATA \mem_r_data
end
would lead to invalid Verilog:
reg [1:0] _0_;
always @(posedge 1'h0) begin
_0_ <= mem_r_addr;
end
assign mem_r_data = mem[_0_];
Note that there are two potential pitfalls remaining after this
change:
* For asynchronous ports, the \EN input and \TRANSPARENT parameter
are silently ignored. (Per discussion in #760 this is the correct
behavior.)
* For synchronous transparent ports, the \EN input is ignored. This
matches the behavior of the $mem simulation cell. Again, see #760.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
Xiretza
whitequark
Eddie Hung
Alberto Gonzalez
Clifford Wolf
Eddie Hung
rafaeltp
acw1251