yosys

Commit Graph

Author	SHA1	Message	Date
Xiretza	17163cf43a	Add flooring modulo operator The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.	2020-05-28 22:59:03 +02:00
Clifford Wolf	f81bf9bdea	Added SMV back-end 'test_cells.sh' script	2015-08-12 12:56:20 +02:00

Author

SHA1

Message

Date

Xiretza

17163cf43a

Add flooring modulo operator

The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.

2020-05-28 22:59:03 +02:00

Clifford Wolf

f81bf9bdea

Added SMV back-end 'test_cells.sh' script

2015-08-12 12:56:20 +02:00

2 Commits