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14052 Commits

Author SHA1 Message Date
Krystine Sherwin 13d7b5fd6a
Docs: Ignore example outputs 2024-10-07 22:01:56 +13:00
Krystine Sherwin 0b1b94d85e
Docs: Clean example outputs 2024-10-07 22:00:28 +13:00
Krystine Sherwin 468a019c30
docs: Makefile tidying 
examples and dots are now orthogonal.
 2024-10-07 21:56:23 +13:00
Krystine Sherwin 2e1181a092
ci: Run make docs on PRs 2024-10-07 21:25:15 +13:00
github-actions[bot] 6155c59d00 Bump version 2024-10-07 00:21:37 +00:00
KrystalDelusion 3534e6b52d
Merge pull request #4632 from tarikgraba/main 
docs: avoid concurrency issues when generating images in parallel
 2024-10-07 10:33:02 +13:00
Krystine Sherwin 571d181fb4
Fix top-level make docs prerequisites 
Add `$(TARGETS)` for gen_examples and gen_images since they need the `yosys` executable.
Add guidelines source files as a prerequisite to docs/source/generated while we're at it.
 2024-10-07 10:26:29 +13:00
Krystine Sherwin d8038c11d1
Add -j flag to make docs CI 2024-10-07 10:07:17 +13:00
TG 5841b44543 docs: Simplify images generation to allow parallel build 
- remove the tidy target from the main target.
  * aux/log file are already excluded in a .gititgnore file
  * allow parallel generation as the tidy target imposes sequential build
 2024-10-06 08:38:16 +02:00
github-actions[bot] 1bf908dea8 Bump version 2024-10-01 00:23:05 +00:00
Miodrag Milanović 500db6acc6
Merge pull request #4621 from RCoeurjoly/roland/get_vcd2fst 
Add "Get vcd2fst" step to test-yosys job
 2024-09-30 21:38:39 +02:00
Roland Coeurjoly 5fca9b867d Add Get vcd2fst step to test-yosys job 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-30 16:25:32 +02:00
github-actions[bot] 59404f8ce5 Bump version 2024-09-30 00:21:26 +00:00
rherveille ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
N. Engelhardt 8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail 2024-09-23 15:19:48 +02:00
github-actions[bot] 4d581a97d6 Bump version 2024-09-18 00:19:41 +00:00
Martin Povišer a553b7c0c7
Merge pull request #3967 from YosysHQ/claire/bufnorm 
Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command
 2024-09-17 11:27:23 +02:00
Martin Povišer eeffca9470 simlib: Add `$buf` disclaimer 2024-09-17 10:46:20 +02:00
Martin Povišer e13ace675e dump: Update help after option removal 2024-09-17 10:46:20 +02:00
Martin Povišer 38de01807e Mark `bufnorm` experimental 2024-09-17 10:46:20 +02:00
Martin Povišer 865df26fac Adjust buf-normalized mode 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 8bb70bac8d Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d027ead4b5 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 4d469f461b Add coarse-grain $buf buffer cell type 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf f4b7ea5fb3 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 32808a0393 Improvements and fixes to "bufnorm" cmd 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d0b5dfa6ef Add bufnorm pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
github-actions[bot] c8846243c2 Bump version 2024-09-17 00:16:41 +00:00
Emil J f8ad371254
Merge pull request #4594 from yrabbit/cpu-wip 
Gowin. Add the EMCU primitive.
 2024-09-16 15:41:14 +02:00
Emil J 52382c6544
Merge pull request #4583 from YosysHQ/emil/clock_gate 
clockgate: centralize clock enables out of FFs
 2024-09-16 15:41:01 +02:00
Emil J. Tywoniak f193bcf683 clockgate: help string 2024-09-16 14:20:33 +02:00
Emil J. Tywoniak be7c93ec6d clockgate: 1-bit const 0 2024-09-16 13:58:27 +02:00
Emil J a8a92d3469
clockgate: help string 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-09-16 13:55:53 +02:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
github-actions[bot] 229d1ea937 Bump version 2024-09-12 00:19:38 +00:00
Emil J. Tywoniak 1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00
Martin Povišer 34572708d5
Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode 
internal_stats: astnode (sizeof)
 2024-09-11 12:21:29 +02:00
Emil J. Tywoniak 1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Emil J. Tywoniak 8b464341c2 clockgate: no initvals 2024-09-11 10:24:48 +02:00
YRabbit ab35dff702 Gowin. Add the EMCU primitive. 
EMCU is a micro-processor based on ARM Cortex-M3 embedded in the
GW1NSR-4C chip used in the Tangnano4k board.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-11 10:18:51 +10:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
github-actions[bot] 6937241012 Bump version 2024-09-10 00:19:34 +00:00
Emil J. Tywoniak 7e473299bd clockgate: bail on constant signals 2024-09-09 21:20:19 +02:00
Emil J. Tywoniak dc039d8be4 clockgate: test fine-grained cells 2024-09-09 21:03:22 +02:00
Emil J. Tywoniak e64fceef70 clockgate: prototype clock gating 2024-09-09 15:00:54 +02:00
Martin Povišer 982fade0df
Merge pull request #4587 from hnpl/main 
Initialize area stats in stat pass
 2024-09-09 07:47:08 +02:00
Hoa Nguyen c1205ebc42 Initialize area stats in stat pass 
Currently, the area variables in the stat struct are not initialized.
This caused the area stats occasionally being an erroneous value.

Signed-off-by: Hoa Nguyen <hnpl@google.com>
 2024-09-07 21:30:58 -07:00
github-actions[bot] dcf9f58315 Bump version 2024-09-07 00:18:42 +00:00
Miodrag Milanović b20df72e1e
Merge pull request #4536 from YosysHQ/functional 
Functional Backend
 2024-09-06 10:05:04 +02:00