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774 Commits

Author SHA1 Message Date
Clifford Wolf 52f80718a7
Merge pull request #848 from YosysHQ/clifford/fix763 
Fix error for wire decl in always block, fixes 763
 2019-03-02 16:32:58 -08:00
Clifford Wolf ae9286386d Only run derive on blackbox modules when ports have dynamic size 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 12:36:46 -08:00
Clifford Wolf 3a51714451 Fix error for wire decl in always block, fixes #763 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 11:56:44 -08:00
Clifford Wolf ce6695e22c Fix $global_clock handling vs autowire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 10:38:13 -08:00
Clifford Wolf 5d93dcce86 Fix $readmem[hb] for mem2reg memories, fixes #785 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 09:58:20 -08:00
Clifford Wolf 7cfae2c52f Use mem2reg on memories that only have constant-index write ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 13:35:09 -08:00
Clifford Wolf 60e3c38054 Improve "read" error msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-28 20:34:42 -08:00
Clifford Wolf 1816fe06af Fix handling of defparam for when default_nettype is none 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:09:41 +01:00
Clifford Wolf a516b4fb5a Check if Verific was built with DB_PRESERVE_INITIAL_VALUE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 19:51:30 +01:00
Clifford Wolf 23148ffae1 Fixes related to handling of autowires and upto-ranges, fixes #814 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 18:40:11 +01:00
Clifford Wolf 974927adcf Fix handling of expression width in $past, fixes #810 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:55:33 +01:00
Clifford Wolf 28fba903c5 Fix segfault in printing of some internal error messages 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:40:52 +01:00
Clifford Wolf 807b3c7697 Fix sign handling of real constants 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-13 12:36:47 +01:00
Clifford Wolf 17ceab92a9 Bugfix in Verilog string handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 12:10:24 +01:00
Clifford Wolf 6d1e7e9403 Remove -m32 Verific eval lib build instructions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-04 15:03:49 +01:00
Clifford Wolf 1eb101a38a Improve VerificImporter support for writes to asymmetric memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:33:43 +01:00
Clifford Wolf 50b09de033 Fix VerificImporter asymmetric memories error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:05:23 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Clifford Wolf 6dad191377 Add "read_ilang -[no]overwrite" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-23 15:45:09 +01:00
Clifford Wolf fdf7c42181 Fix segfault in AST simplify 
(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 17:49:38 +01:00
Clifford Wolf 3d671630e2 Improve src tagging (using names and attrs) of cells and wires in verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 16:01:22 +01:00
whitequark 4effb38e6d read_ilang: allow slicing sigspecs. 2018-12-16 17:53:26 +00:00
Sylvain Munaut 58fb2ac818 verilog_parser: Properly handle recursion when processing attributes 
Fixes #737

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-12-14 12:48:00 +01:00
Clifford Wolf 910d94b212 Verific updates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:21:50 +01:00
Sylvain Munaut 86ce43999e Make return value of $clog2 signed 
As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-24 18:49:23 +01:00
Clifford Wolf 5387ccb041 Set Verific flag vhdl_support_variable_slice=1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 21:03:23 +01:00
Clifford Wolf 719e29404a Allow square brackets in liberty identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-05 12:33:33 +01:00
Clifford Wolf 36ea98385f Add warning for SV "restrict" without "property" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 15:57:17 +01:00
Clifford Wolf 64e0582c29 Various indenting fixes in AST front-end (mostly space vs tab issues) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 10:19:32 +01:00
ZipCPU 39f891aebc Make and dependent upon LSB only 2018-11-03 13:39:32 -04:00
Clifford Wolf d86ea6badd Do not generate "reg assigned in a continuous assignment" warnings for "rand reg" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-01 15:25:24 +01:00
Clifford Wolf 5ab58d4930 Fix minor typo in error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-25 13:20:00 +02:00
Clifford Wolf 6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error 
More meaningful SystemVerilog/Verilog parser error messages
 2018-10-25 13:18:59 +02:00
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00
Clifford Wolf 23b69ca32b Improve read_verilog range out of bounds warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-20 23:48:53 +02:00
Ruben Undheim 436e3c0a7c Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim d9a4381012 Fixed memory leak 2018-10-20 11:57:39 +02:00
Clifford Wolf f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
Clifford Wolf 93d99559ef
Merge pull request #664 from tklam/ignore-verilog-protect 
Ignore protect endprotect
 2018-10-18 10:52:07 +02:00
Clifford Wolf 6ca493b88c Minor code cleanups in liberty front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-17 12:23:36 +02:00
Clifford Wolf 8395c18cb5
Merge pull request #660 from tklam/parse-liberty-detect-ff-latch 
Handling ff/latch in liberty files
 2018-10-17 12:21:17 +02:00
Clifford Wolf 38dbb44fa0
Merge pull request #638 from udif/pr_reg_wire_error 
Fix issue #630
 2018-10-17 12:13:18 +02:00
argama 097da32e1a ignore protect endprotect 2018-10-16 21:33:37 +08:00
Ruben Undheim 736105b046 Handle FIXME for modport members without type directly in front 2018-10-13 20:50:33 +02:00
Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
argama 455638e00d detect ff/latch before processing other nodes 2018-10-14 01:42:48 +08:00
Ruben Undheim a36d1701dd Fix build error with clang 2018-10-12 22:14:49 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00