Eddie Hung
|
162eab6b74
|
Combine techmap calls
|
2019-08-08 10:55:48 -07:00 |
Eddie Hung
|
7160243874
|
Move xilinx_dsp to before alumacc
|
2019-08-08 10:45:56 -07:00 |
Eddie Hung
|
57b2e4b9c1
|
INMODE is 5 bits
|
2019-08-08 10:44:35 -07:00 |
Eddie Hung
|
13cc106cf7
|
Fix copy-pasta typo
|
2019-08-08 10:44:26 -07:00 |
David Shah
|
b8cd4ad64a
|
DSP48E1 sim model: add SIMD tests
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-08 11:39:35 +01:00 |
David Shah
|
57aeb4cc01
|
DSP48E1 model: test CE inputs
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-08 11:32:43 +01:00 |
David Shah
|
d60b3c0dc8
|
DSP48E1 sim model: fix seq tests and add preadder tests
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-08 11:18:37 +01:00 |
David Shah
|
e7dbe7bb3d
|
DSP48E1 sim model: seq test working
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-08 10:52:04 +01:00 |
David Shah
|
f6605c7dc0
|
DSP48E1 sim model: Comb, no pre-adder, mode working
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-08 10:26:44 +01:00 |
David Shah
|
f0f352e971
|
[wip] sim model testing
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-08 10:05:11 +01:00 |
David Shah
|
ccfb4ff2a9
|
[wip] sim model testing
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-08 09:31:34 +01:00 |
Eddie Hung
|
48d0f99406
|
stoi -> atoi
|
2019-08-07 11:09:17 -07:00 |
David Shah
|
fe95807f16
|
[wip] DSP48E1 sim model improvements
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-07 13:09:12 +01:00 |
David Shah
|
c43b0c4b49
|
[wip] DSP48E1 sim model improvements
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-06 18:47:18 +01:00 |
David Shah
|
7a563d0b92
|
[wip] DSP48E1 sim model improvements
Signed-off-by: David Shah <dave@ds0.me>
|
2019-08-06 13:23:42 +01:00 |
Eddie Hung
|
fc0b5d5ab6
|
Change $__softmul back to $mul
|
2019-08-01 12:45:14 -07:00 |
Eddie Hung
|
ed303b07b7
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-01 12:02:16 -07:00 |
Eddie Hung
|
66806085db
|
RST -> RSTBRST for RAMB8BWER
|
2019-07-29 16:05:44 -07:00 |
David Shah
|
ab607e896e
|
xilinx: Fix missing cell name underscore in cells_map.v
Signed-off-by: David Shah <dave@ds0.me>
|
2019-07-25 08:19:07 +01:00 |
Eddie Hung
|
601fac97e4
|
Add params
|
2019-07-18 21:02:49 -07:00 |
Eddie Hung
|
43616e1414
|
Update Makefile too
|
2019-07-18 14:51:55 -07:00 |
Eddie Hung
|
b97fe6e866
|
Work in progress for renaming labels/options in synth_xilinx
|
2019-07-18 14:20:43 -07:00 |
Eddie Hung
|
5562cb08a4
|
Use single DSP_SIGNEDONLY macro
|
2019-07-18 13:09:55 -07:00 |
Eddie Hung
|
e3f8e59f18
|
Make all operands signed
|
2019-07-17 14:25:40 -07:00 |
Eddie Hung
|
58e63feae1
|
Update comment
|
2019-07-17 13:26:17 -07:00 |
Eddie Hung
|
c501aa5ee8
|
Signedness
|
2019-07-16 15:54:27 -07:00 |
Eddie Hung
|
6390c535ba
|
Revert drop down to 24x16 multipliers for all
|
2019-07-16 14:30:25 -07:00 |
Eddie Hung
|
569cd66764
|
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
|
2019-07-16 14:18:36 -07:00 |
Eddie Hung
|
5d1ce04381
|
Add support for {A,B,P}REG in DSP48E1
|
2019-07-16 14:05:50 -07:00 |
David Shah
|
d38df68d26
|
xilinx: Add correct signed behaviour to DSP48E1 model
Signed-off-by: David Shah <dave@ds0.me>
|
2019-07-16 17:53:08 +01:00 |
David Shah
|
95c8d27b0b
|
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
Signed-off-by: David Shah <dave@ds0.me>
|
2019-07-16 16:47:53 +01:00 |
Eddie Hung
|
5f00d335d4
|
Oops forgot these files
|
2019-07-15 15:03:15 -07:00 |
Eddie Hung
|
0c7ee6d0fa
|
Move DSP mapping back out to dsp_map.v
|
2019-07-15 14:18:44 -07:00 |
Eddie Hung
|
20e3d2d9b0
|
Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim
|
2019-07-15 11:13:22 -07:00 |
Eddie Hung
|
146451a767
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-07-15 09:49:41 -07:00 |
Eddie Hung
|
1c9f3fadb9
|
Add Tsu offset to boxes, and comments
|
2019-07-11 17:17:26 -07:00 |
Eddie Hung
|
d386177e6d
|
ABC doesn't like negative delays in flop boxes...
|
2019-07-11 17:09:17 -07:00 |
Eddie Hung
|
3ef927647c
|
Fix FDCE_1 box
|
2019-07-11 14:25:47 -07:00 |
Eddie Hung
|
1ada568134
|
Revert "$pastQ should be first input"
This reverts commit 8f9d529929 .
|
2019-07-11 14:23:45 -07:00 |
Eddie Hung
|
854333f2af
|
Propagate INIT attr
|
2019-07-11 13:55:47 -07:00 |
Eddie Hung
|
8f9d529929
|
$pastQ should be first input
|
2019-07-11 13:54:40 -07:00 |
Eddie Hung
|
021f8e5492
|
Fix typo
|
2019-07-11 13:23:07 -07:00 |
Eddie Hung
|
19c1c3cfa3
|
Merge pull request #1182 from koriakin/xc6s-bram
synth_xilinx: Initial Spartan 6 block RAM inference support.
|
2019-07-11 12:55:35 -07:00 |
Marcin Kościelnicki
|
a9efacd01d
|
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
|
2019-07-11 21:13:12 +02:00 |
Eddie Hung
|
8fef4c3594
|
Simplify to $__ABC_ASYNC box
|
2019-07-11 10:52:33 -07:00 |
Eddie Hung
|
93fbd56db1
|
$__ABC_FD_ASYNC_MUX.Q -> Y
|
2019-07-11 10:25:59 -07:00 |
Marcin Kościelnicki
|
ce250b341c
|
synth_xilinx: Initial Spartan 6 block RAM inference support.
|
2019-07-11 14:45:48 +02:00 |
Eddie Hung
|
d357431df1
|
Restore from master
|
2019-07-10 22:54:39 -07:00 |
Eddie Hung
|
f984e0cb34
|
Another typo
|
2019-07-10 22:33:35 -07:00 |
Eddie Hung
|
ea6ffea2cd
|
Fix clk_pol for FD*_1
|
2019-07-10 20:10:20 -07:00 |
Eddie Hung
|
7899a06ed6
|
Another typo
|
2019-07-10 19:59:24 -07:00 |
Eddie Hung
|
ad35b509de
|
Another typo
|
2019-07-10 19:05:53 -07:00 |
Eddie Hung
|
f3511e4f93
|
Use \$currQ
|
2019-07-10 19:01:13 -07:00 |
Eddie Hung
|
f030be3f1c
|
Preserve all parameters, plus some extra ones for clk/en polarity
|
2019-07-10 18:57:11 -07:00 |
Eddie Hung
|
4a995c5d80
|
Change how to specify flops to ABC again
|
2019-07-10 17:54:56 -07:00 |
Eddie Hung
|
3bb48facb2
|
Remove params from FD*_1 variants
|
2019-07-10 17:17:54 -07:00 |
Eddie Hung
|
0372c900e8
|
Fix typo, and have !{PRE,CLR} behave as CE
|
2019-07-10 17:15:49 -07:00 |
Eddie Hung
|
7b2599cb94
|
Move ABC FF stuff to abc_ff.v; add support for other FD* types
|
2019-07-10 17:06:05 -07:00 |
Eddie Hung
|
0ab8f28bc7
|
Uncomment IS_C_INVERTED parameter
|
2019-07-10 16:23:15 -07:00 |
Eddie Hung
|
838ae1a14c
|
synth_xilinx's map_cells stage to techmap ff_map.v
|
2019-07-10 16:15:57 -07:00 |
Eddie Hung
|
73c8f1a59e
|
Fix box numbering
|
2019-07-10 16:12:33 -07:00 |
Eddie Hung
|
052060f109
|
Merge remote-tracking branch 'origin/master' into xaig_dff
|
2019-07-10 16:05:41 -07:00 |
Eddie Hung
|
b33ecd2a74
|
Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little
|
2019-07-10 16:00:03 -07:00 |
Eddie Hung
|
cea7441d8a
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-07-10 15:58:01 -07:00 |
Eddie Hung
|
bb2144ae73
|
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Error out if -abc9 and -retime specified
|
2019-07-10 14:38:13 -07:00 |
Eddie Hung
|
6bbd286e03
|
Error out if -abc9 and -retime specified
|
2019-07-10 12:47:48 -07:00 |
Eddie Hung
|
58bb84e5b2
|
Add some spacing
|
2019-07-10 12:32:33 -07:00 |
Eddie Hung
|
521971e32e
|
Add some ASCII art explaining mux decomposition
|
2019-07-10 12:20:04 -07:00 |
Eddie Hung
|
e573d024a2
|
Call muxpack and pmux2shiftx before cmp2lut
|
2019-07-09 21:26:38 -07:00 |
Eddie Hung
|
c55530b901
|
Restore opt_clean back to original place
|
2019-07-09 14:29:58 -07:00 |
Eddie Hung
|
5b48b18d29
|
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
|
2019-07-09 14:28:54 -07:00 |
Eddie Hung
|
b1a048a703
|
Extend using A[1] to preserve don't care
|
2019-07-09 12:35:41 -07:00 |
Eddie Hung
|
93522b0ae1
|
Extend during mux decomposition with 1'bx
|
2019-07-09 10:59:37 -07:00 |
Eddie Hung
|
c864995343
|
Fix typo and comments
|
2019-07-09 10:38:07 -07:00 |
Eddie Hung
|
c91cb73562
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-07-09 10:22:49 -07:00 |
Eddie Hung
|
c68b909210
|
synth_xilinx to call commands of synth -coarse directly
|
2019-07-09 10:21:54 -07:00 |
Eddie Hung
|
737340327f
|
Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
This reverts commit 7f964859ec .
|
2019-07-09 10:15:02 -07:00 |
Eddie Hung
|
bc84f7dd10
|
Fix spacing
|
2019-07-09 09:22:12 -07:00 |
Eddie Hung
|
667199d460
|
Fix spacing
|
2019-07-09 09:16:00 -07:00 |
Eddie Hung
|
6951e32070
|
Decompose mux inputs in delay-orientated (rather than area) fashion
|
2019-07-08 23:51:13 -07:00 |
Eddie Hung
|
45da3ada7b
|
Do not call opt -mux_undef (part of -full) before muxcover
|
2019-07-08 23:49:16 -07:00 |
Eddie Hung
|
d4ab43d940
|
Add one more comment
|
2019-07-08 23:05:48 -07:00 |
Eddie Hung
|
939a225f92
|
Less thinking
|
2019-07-08 23:02:57 -07:00 |
Eddie Hung
|
de40453553
|
Reword
|
2019-07-08 22:56:19 -07:00 |
Eddie Hung
|
7f964859ec
|
synth_xilinx to call "synth -run coarse" with "-keepdc"
|
2019-07-08 19:23:24 -07:00 |
Eddie Hung
|
3f86407cc3
|
Map $__XILINX_SHIFTX in a more balanced manner
|
2019-07-08 17:06:35 -07:00 |
Eddie Hung
|
78914e2e0e
|
Capitalisation
|
2019-07-08 17:06:22 -07:00 |
Eddie Hung
|
baf47e496f
|
Add synth_xilinx -widemux recommended value
|
2019-07-08 17:04:39 -07:00 |
Eddie Hung
|
895ca50173
|
Fixes for 2:1 muxes
|
2019-07-08 12:03:38 -07:00 |
Eddie Hung
|
0944acf3af
|
synth_xilinx -widemux=2 is minimum now
|
2019-07-08 11:29:21 -07:00 |
David Shah
|
c865559f95
|
xc7: Map combinational DSP48E1s
Signed-off-by: David Shah <dave@ds0.me>
|
2019-07-08 19:15:25 +01:00 |
Eddie Hung
|
dbe1326573
|
Parametric muxcover costs as per @daveshah1
|
2019-07-08 11:08:20 -07:00 |
Eddie Hung
|
c58998a7d2
|
atoi -> stoi as per @daveshah1
|
2019-07-08 10:48:10 -07:00 |
Eddie Hung
|
810f8c5dbd
|
Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup
|
2019-07-02 09:21:02 -07:00 |
Eddie Hung
|
2ea6083b7e
|
Fix $__XILINX_MUXF78 box timing
|
2019-07-01 14:04:06 -07:00 |
Eddie Hung
|
09ac274716
|
Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
This reverts commit a9a140aa6c .
|
2019-07-01 14:01:09 -07:00 |
Eddie Hung
|
a9a140aa6c
|
Fix broken MUXFx box, use MUXF7x2 box instead
|
2019-07-01 13:36:27 -07:00 |
Eddie Hung
|
5466121ffb
|
Capture all data in one "abc_flop" attribute
|
2019-07-01 11:50:14 -07:00 |
Eddie Hung
|
659c04a68d
|
Update abc_box_id numbering
|
2019-07-01 10:47:14 -07:00 |
Eddie Hung
|
699d8e3939
|
Merge remote-tracking branch 'origin/master' into xaig_dff
|
2019-07-01 10:44:42 -07:00 |
Eddie Hung
|
85f1c2dcbe
|
Cleanup SRL inference/make more consistent
|
2019-06-29 21:42:20 -07:00 |
Eddie Hung
|
62ba724ccb
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-06-29 19:39:27 -07:00 |
Eddie Hung
|
dd8d264bf5
|
install *_nowide.lut files
|
2019-06-29 19:37:04 -07:00 |
Eddie Hung
|
728839d6ca
|
Remove peepopt call in synth_xilinx since already in synth -run coarse
|
2019-06-28 12:53:38 -07:00 |
Eddie Hung
|
ea0f7c9be9
|
Restore $__XILINX_MUXF78 const optimisation
|
2019-06-28 12:12:41 -07:00 |
Eddie Hung
|
a193bf27c9
|
Clean up trimming leading 1'bx in A during techmappnig
|
2019-06-28 12:03:43 -07:00 |
Eddie Hung
|
cf020befeb
|
Fix CARRY4 abc_box_id
|
2019-06-28 11:28:50 -07:00 |
Eddie Hung
|
4ef26d4755
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-06-28 11:09:42 -07:00 |
Eddie Hung
|
00f63d82ce
|
Reduce diff with upstream
|
2019-06-27 16:13:22 -07:00 |
Eddie Hung
|
9398921af1
|
Refactor for one "abc_carry" attribute on module
|
2019-06-27 16:07:14 -07:00 |
Eddie Hung
|
312c03e4ca
|
Remove redundant doc
|
2019-06-27 15:28:55 -07:00 |
Eddie Hung
|
4d00e27ed7
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-27 11:23:30 -07:00 |
Eddie Hung
|
1237a4c116
|
Add warning if synth_xilinx -abc9 with family != xc7
|
2019-06-27 11:22:49 -07:00 |
Eddie Hung
|
6c256b8cda
|
Merge origin/master
|
2019-06-27 11:20:15 -07:00 |
Eddie Hung
|
593e4a30bb
|
MUXF78 -> $__MUXF78 to indicate internal
|
2019-06-26 20:09:28 -07:00 |
Eddie Hung
|
dbb8c8caaa
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-26 20:07:31 -07:00 |
Eddie Hung
|
a7a88109f5
|
Update comment on boxes
|
2019-06-26 20:00:15 -07:00 |
Eddie Hung
|
b7bef15b16
|
Add "WE" to dist RAM's abc_scc_break
|
2019-06-26 19:58:09 -07:00 |
Eddie Hung
|
b9ff0503f3
|
synth_xilinx's muxcover call to be very conservative -- -nodecode
|
2019-06-26 17:57:10 -07:00 |
Eddie Hung
|
f0a1726a1a
|
Accidentally removed "simplemap $mux"
|
2019-06-26 17:48:49 -07:00 |
Eddie Hung
|
2b104ed6c8
|
Replace with <internal options>
|
2019-06-26 17:42:50 -07:00 |
Eddie Hung
|
cae69a3edd
|
Rework help_mode for synth_xilinx -widemux
|
2019-06-26 17:41:21 -07:00 |
Eddie Hung
|
5f807a7a5b
|
Return to upstream synth_xilinx with opt -full and wreduce
|
2019-06-26 16:25:48 -07:00 |
Eddie Hung
|
812469aaa3
|
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
|
2019-06-26 14:48:35 -07:00 |
Eddie Hung
|
c762be5930
|
Instead of blocking wreduce on $mux, use -keepdc instead #1132
|
2019-06-26 11:48:35 -07:00 |
Eddie Hung
|
8d8261c71f
|
Do not call opt with -full before muxcover
|
2019-06-26 11:38:28 -07:00 |
Eddie Hung
|
80de03a7a6
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-26 11:24:39 -07:00 |
Eddie Hung
|
4d0014d1b1
|
Cleanup abc_box_id
|
2019-06-26 11:23:57 -07:00 |
Eddie Hung
|
612083a807
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-26 10:33:54 -07:00 |
Eddie Hung
|
5e1b8d458b
|
Remove unused var
|
2019-06-26 10:33:07 -07:00 |
Eddie Hung
|
988e6163ab
|
Add _nowide variants of LUT libraries in -nowidelut flows
|
2019-06-26 10:23:29 -07:00 |
Eddie Hung
|
799b18263f
|
Merge branch 'koriakin/xc7nocarrymux' into xaig
|
2019-06-26 10:04:01 -07:00 |
Miodrag Milanovic
|
ea0b6258ab
|
Simulation model verilog fix
|
2019-06-26 18:34:34 +02:00 |
Eddie Hung
|
7389b043c0
|
Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux
|
2019-06-26 09:33:38 -07:00 |
Eddie Hung
|
177c26ca35
|
Rename -minmuxf to -widemux
|
2019-06-26 09:16:45 -07:00 |
Eddie Hung
|
480a04cb3c
|
Realistic delays for RAM32X1D too
|
2019-06-25 09:34:28 -07:00 |
Eddie Hung
|
6095357390
|
Add RAM32X1D box info
|
2019-06-25 09:34:19 -07:00 |
Eddie Hung
|
6f36ec8ecf
|
Merge remote-tracking branch 'origin/master' into xaig
|
2019-06-25 09:33:11 -07:00 |
Eddie Hung
|
4238feed81
|
This optimisation doesn't seem to work...
|
2019-06-25 09:21:46 -07:00 |
Eddie Hung
|
158325956e
|
Realistic delays for RAM32X1D too
|
2019-06-24 23:05:28 -07:00 |
Eddie Hung
|
3825068a75
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-24 23:04:25 -07:00 |
Eddie Hung
|
2f770b7400
|
Use LUT delays for dist RAM delays
|
2019-06-24 23:02:53 -07:00 |
Eddie Hung
|
e1ba25d79f
|
Add RAM32X1D box info
|
2019-06-24 22:54:35 -07:00 |
Eddie Hung
|
1564eb8b54
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-24 22:48:49 -07:00 |
Eddie Hung
|
152e682bd5
|
Add Xilinx dist RAM as comb boxes
|
2019-06-24 21:54:01 -07:00 |
Eddie Hung
|
f1675b88f6
|
Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
|
2019-06-24 16:39:18 -07:00 |
Eddie Hung
|
efd04880db
|
Add RAM32X1D support
|
2019-06-24 16:16:50 -07:00 |
Eddie Hung
|
c3df895bf4
|
Reduce MuxFx resources in mux techmapping
|
2019-06-24 15:16:44 -07:00 |
Eddie Hung
|
db6a0b72b2
|
Reduce number of decomposed muxes during techmap
|
2019-06-24 14:28:56 -07:00 |
Eddie Hung
|
2e7992efff
|
Revert "Fix techmapping muxes some more"
This reverts commit 0aae3b4f43 .
|
2019-06-24 14:15:31 -07:00 |
Eddie Hung
|
7fbfcf20d1
|
Move comment
|
2019-06-24 14:15:00 -07:00 |
Eddie Hung
|
0aae3b4f43
|
Fix techmapping muxes some more
|
2019-06-24 12:50:48 -07:00 |
Eddie Hung
|
2b4501503d
|
Fix mux techmapping
|
2019-06-24 12:18:17 -07:00 |
Eddie Hung
|
aa1eeda567
|
Modify costs for muxcover
|
2019-06-24 11:51:55 -07:00 |
Eddie Hung
|
36e6da5396
|
Change synth_xilinx's -nomux to -minmuxf <int>
|
2019-06-24 10:04:01 -07:00 |
Eddie Hung
|
d54dceb547
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-22 19:44:17 -07:00 |
Eddie Hung
|
792d0670c3
|
Add comment to xc7 box
|
2019-06-22 14:28:24 -07:00 |
Eddie Hung
|
7903ebe3e0
|
Carry in/out box ordering now move to end, not swap with end
|
2019-06-22 14:18:42 -07:00 |
Eddie Hung
|
65c022c257
|
Remove DFF and RAMD box info for now
|
2019-06-21 20:41:14 -07:00 |
Eddie Hung
|
bbf3ad90f5
|
Remove $_MUX4_ techmap rule
|
2019-06-21 18:12:33 -07:00 |
Eddie Hung
|
39e0e006d5
|
Fix wreduce call (!!!), tweak muxcover costs
|
2019-06-21 18:12:07 -07:00 |
Eddie Hung
|
faa2d6fc1c
|
Constrain wreduce only if wide mux
|
2019-06-21 17:12:34 -07:00 |
Eddie Hung
|
aeee9dcad7
|
Simplify and comment out mux_map.v
|
2019-06-21 17:06:30 -07:00 |
Eddie Hung
|
ed00823b41
|
synth_xilinx to now wreduce except $mux, remove extra peepopt
|
2019-06-21 16:56:56 -07:00 |
Eddie Hung
|
29aee0989f
|
mux_map to no longer copy last value into 1'bx
|
2019-06-21 16:55:59 -07:00 |
Eddie Hung
|
8bce3fb329
|
Fix spacing
|
2019-06-21 16:55:34 -07:00 |
Eddie Hung
|
694d40719f
|
Fix spacing again, A_forward -> A_backward
|
2019-06-21 16:47:07 -07:00 |
Eddie Hung
|
11886c874c
|
Restore wreduce to synth_xilinx, after muxcover
|
2019-06-21 16:18:29 -07:00 |
Eddie Hung
|
44fc616fc7
|
Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
|
2019-06-21 16:18:14 -07:00 |
Eddie Hung
|
4d6fac019a
|
Fix spacing
|
2019-06-21 16:06:13 -07:00 |
Eddie Hung
|
aa0b107afb
|
synth_xilinx to use _ABC macro, and perform muxpack again
|
2019-06-21 15:48:20 -07:00 |
Eddie Hung
|
9abde12110
|
Add $__XILINX_MUXF78 to preserve entire box
|
2019-06-21 15:47:42 -07:00 |
Eddie Hung
|
7acbea6b28
|
Fix alignment
|
2019-06-21 14:38:30 -07:00 |
Eddie Hung
|
f433a52374
|
Add FIXME about need for -mux4
|
2019-06-21 11:15:23 -07:00 |
Eddie Hung
|
c6b4653ebe
|
Since muxcover uses MUX4s, blast them back to gates here
|
2019-06-21 11:13:01 -07:00 |
Eddie Hung
|
dd22edcd28
|
Expand synth -coarse without wreduce, move muxcover
|
2019-06-21 11:12:32 -07:00 |
Eddie Hung
|
f11c9a419b
|
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
|
2019-06-20 17:38:16 -07:00 |
Eddie Hung
|
d1dadfcec8
|
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
|
2019-06-20 16:45:09 -07:00 |
Eddie Hung
|
9faab38e8d
|
mux_map to drop sign bit, and eliminate 'bx-es
|
2019-06-20 16:45:04 -07:00 |
Eddie Hung
|
4ca847a217
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-18 11:49:54 -07:00 |
Eddie Hung
|
8e0a47fb92
|
Really permute Xilinx LUT mappings as default LUT6.I5:A6
|
2019-06-18 11:48:48 -07:00 |
Eddie Hung
|
8f5e6d73ff
|
Revert "Fix (do not) permute LUT inputs, but permute mux selects"
This reverts commit da3d2eedd2 .
|
2019-06-18 11:35:21 -07:00 |
Eddie Hung
|
3d283e69f8
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-18 09:51:28 -07:00 |
Eddie Hung
|
da3d2eedd2
|
Fix (do not) permute LUT inputs, but permute mux selects
|
2019-06-18 09:49:57 -07:00 |
Eddie Hung
|
2b0e28b261
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-17 22:29:34 -07:00 |
Eddie Hung
|
608a95eb01
|
Fix copy-pasta issue
|
2019-06-17 22:29:22 -07:00 |
Eddie Hung
|
59b4e69d16
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-17 22:25:14 -07:00 |
Eddie Hung
|
2a35c4ef94
|
Permute INIT for +/xilinx/lut_map.v
|
2019-06-17 22:24:35 -07:00 |
Eddie Hung
|
75f8b4cf10
|
Simplify comment
|
2019-06-17 19:14:41 -07:00 |
Eddie Hung
|
75d92fb590
|
Merge branch 'xaig' into xaig_dff
|
2019-06-17 19:11:07 -07:00 |
Eddie Hung
|
9d56c0d525
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-17 18:25:35 -07:00 |
Eddie Hung
|
840562943f
|
Update LUT7/8 delays to take account for [ABC]OUTMUX delay
|
2019-06-17 17:06:01 -07:00 |
Eddie Hung
|
8a86f9bb62
|
Add box delays for FD*
|
2019-06-17 15:13:05 -07:00 |
Eddie Hung
|
5ce672d1c5
|
Merge remote-tracking branch 'origin/xaig' into xaig_dff
|
2019-06-17 12:14:55 -07:00 |
Eddie Hung
|
c15ee827f4
|
Try -W 300
|
2019-06-17 10:29:06 -07:00 |
Eddie Hung
|
1ec450d6bf
|
Try -W 300
|
2019-06-16 12:08:03 -07:00 |
Eddie Hung
|
0c59bc0b75
|
Cleanup
|
2019-06-16 10:42:00 -07:00 |
Eddie Hung
|
d969a9060e
|
Add +/xilinx/abc_ff
|
2019-06-15 22:41:29 -07:00 |
Eddie Hung
|
9ec57b46c2
|
Fix spacing
|
2019-06-15 19:36:37 -07:00 |
Eddie Hung
|
c2f3f116d0
|
Use $__ABC_FF_ instead of $_FF_
|
2019-06-15 18:16:14 -07:00 |
Eddie Hung
|
65c7bafc64
|
Re-order alphabetically
|
2019-06-15 10:19:05 -07:00 |
Eddie Hung
|
a76c8a7ffd
|
Fix initialisation of flops
|
2019-06-15 09:46:35 -07:00 |
Eddie Hung
|
ac18a76beb
|
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
|
2019-06-15 09:34:48 -07:00 |
Eddie Hung
|
295bb23ae0
|
Wrap FDRE with $__ABC_FDRE containing comb
|
2019-06-15 09:08:56 -07:00 |
Eddie Hung
|
842c110357
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-15 05:48:47 -07:00 |
Eddie Hung
|
bf312043d4
|
Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
|
2019-06-15 05:45:16 -07:00 |
Eddie Hung
|
b63b2a0bd4
|
Revert "Remove wide mux inference"
This reverts commit 738fdfe8f5 .
|
2019-06-14 12:50:24 -07:00 |
Eddie Hung
|
8fa74287a7
|
As per @daveshah1 remove async DFF timing from xilinx
|
2019-06-14 12:43:20 -07:00 |
Eddie Hung
|
2e34859a6b
|
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
|
2019-06-14 11:38:22 -07:00 |
Eddie Hung
|
ba4b4a0088
|
Update delays based on SymbiFlow/prjxray-db
|
2019-06-14 11:33:10 -07:00 |
Eddie Hung
|
d47ff7ba87
|
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
|
2019-06-14 10:51:11 -07:00 |
Eddie Hung
|
ee428f73ab
|
Remove WIP ABC9 flop support
|
2019-06-14 10:37:52 -07:00 |
Eddie Hung
|
627a62a797
|
Make doc consistent
|
2019-06-14 10:32:46 -07:00 |
Eddie Hung
|
75d89e56cf
|
Fix name clash
|
2019-06-13 14:27:07 -07:00 |
Eddie Hung
|
009255d11d
|
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
|
2019-06-12 16:07:24 -07:00 |
Eddie Hung
|
c7f5091c2f
|
Reduce diff with master
|
2019-06-12 09:34:41 -07:00 |
Eddie Hung
|
99267f660f
|
Fix spacing
|
2019-06-12 09:21:52 -07:00 |
Eddie Hung
|
738fdfe8f5
|
Remove wide mux inference
|
2019-06-12 09:20:46 -07:00 |
Eddie Hung
|
1e838a8913
|
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
|
2019-06-12 08:49:15 -07:00 |
Eddie Hung
|
4c9fde87d1
|
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
This reverts commit 2dffa4685b .
|
2019-06-12 08:48:45 -07:00 |
Eddie Hung
|
2dffa4685b
|
Add "-W' wire delay arg to abc9, use from synth_xilinx
|
2019-06-11 17:10:47 -07:00 |
Eddie Hung
|
54379f9872
|
Disable dist RAM boxes due to comb loop
|
2019-06-11 12:02:51 -07:00 |
Eddie Hung
|
8a708d1fdb
|
Remove #ifndef ABC
|
2019-06-11 12:02:31 -07:00 |
Eddie Hung
|
b77c5da769
|
Revert "Revert "Move ff_map back after ABC for shregmap""
This reverts commit e473e74565 .
|
2019-06-10 14:37:09 -07:00 |
Eddie Hung
|
a1d4ae78a0
|
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
This reverts commit 94a5f4e609 .
|
2019-06-10 14:34:43 -07:00 |
Eddie Hung
|
816b5f5891
|
Comment out muxpack (currently broken)
|
2019-06-07 16:58:57 -07:00 |
Eddie Hung
|
88ae13e6a5
|
$__XILINX_MUX_ -> $__XILINX_SHIFTX
|
2019-06-06 15:32:36 -07:00 |
Eddie Hung
|
d3b7ae218b
|
Fix muxcover and its techmapping
|
2019-06-06 15:31:18 -07:00 |
Eddie Hung
|
a8c49168fb
|
Run muxpack and muxcover in synth_xilinx
|
2019-06-06 14:43:08 -07:00 |
Eddie Hung
|
7166dbe418
|
Remove abc_flop attributes for now
|
2019-06-06 14:35:38 -07:00 |
Eddie Hung
|
6ed15b7890
|
Update abc attributes on FD*E_1
|
2019-06-05 12:33:40 -07:00 |
Eddie Hung
|
67f744d428
|
Cleanup
|
2019-06-05 12:28:46 -07:00 |
Eddie Hung
|
2c18d530ea
|
Call shregmap -tech xilinx_static
|
2019-06-05 12:28:26 -07:00 |
Eddie Hung
|
e473e74565
|
Revert "Move ff_map back after ABC for shregmap"
This reverts commit 9b9bd4e19f .
|
2019-06-05 11:53:06 -07:00 |
Eddie Hung
|
94a5f4e609
|
Rename shregmap -tech xilinx -> xilinx_dynamic
|
2019-06-04 14:34:36 -07:00 |
Eddie Hung
|
82d41bc2f2
|
Add space between -D and _ABC
|
2019-06-04 11:54:08 -07:00 |
Eddie Hung
|
f0e93f33cf
|
Add (* abc_flop_q *) to brams_bb.v
|
2019-06-04 11:53:51 -07:00 |
Eddie Hung
|
6cf092641f
|
Fix name clash
|
2019-06-04 09:56:36 -07:00 |
Eddie Hung
|
e260150321
|
Add mux_map.v for wide mux
|
2019-06-04 09:51:47 -07:00 |
Eddie Hung
|
9b9bd4e19f
|
Move ff_map back after ABC for shregmap
|
2019-06-03 23:43:23 -07:00 |
Eddie Hung
|
09b778744d
|
Respect -nocarry
|
2019-06-03 23:42:30 -07:00 |
Eddie Hung
|
5afa42432f
|
Fix pmux2shiftx logic
|
2019-06-03 23:29:45 -07:00 |
Eddie Hung
|
23a73ca624
|
Merge mistake
|
2019-06-03 23:19:22 -07:00 |
Eddie Hung
|
f81a0ed92e
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-06-03 23:07:08 -07:00 |
Eddie Hung
|
b6e59741ae
|
Typo
|
2019-06-03 20:21:41 -07:00 |
Eddie Hung
|
02973474df
|
Remove extra newline
|
2019-06-03 20:04:47 -07:00 |
Eddie Hung
|
c9a0bac541
|
IS_C_INVERTED
|
2019-06-03 19:45:56 -07:00 |
Eddie Hung
|
0ad50332d9
|
Execute techmap and arith_map simultaneously
|
2019-06-03 19:36:09 -07:00 |
Eddie Hung
|
ebcc85b9b8
|
Fix `ifndef
|
2019-06-03 12:37:02 -07:00 |
Eddie Hung
|
2228cef62f
|
Add flops as blackboxes
|
2019-05-31 18:11:46 -07:00 |
Eddie Hung
|
01f71085f2
|
Add FD*E_1 -> FD*E techmap rules
|
2019-05-31 18:11:24 -07:00 |
Eddie Hung
|
dea36d4366
|
Techmap flops before ABC again
|
2019-05-31 18:10:25 -07:00 |
Eddie Hung
|
eb08e71bd1
|
Merge branch 'xaig' into xc7mux
|
2019-05-31 13:03:03 -07:00 |
Eddie Hung
|
1ad33c3b5a
|
Remove whitebox attribute from DRAMs for now
|
2019-05-30 13:07:29 -07:00 |
Eddie Hung
|
fdfc18be91
|
Carry in/out to be the last input/output for chains to be preserved
|
2019-05-30 01:23:36 -07:00 |
Eddie Hung
|
276f5f8b81
|
Some more realistic delays...
|
2019-05-29 22:55:34 -07:00 |
Eddie Hung
|
f228621b80
|
Typo
|
2019-05-28 09:36:01 -07:00 |
Eddie Hung
|
e032e5bcde
|
Make MUXF{7,8} and CARRY4 whitebox
|
2019-05-27 23:09:06 -07:00 |
Eddie Hung
|
54e28eb3ea
|
Re-enable lib_whitebox
|
2019-05-27 23:08:55 -07:00 |
Eddie Hung
|
4311b9b583
|
Blackboxes
|
2019-05-26 11:32:02 -07:00 |
Eddie Hung
|
66701c5fcc
|
Muck about with LUT delays some more
|
2019-05-26 02:52:48 -07:00 |
Eddie Hung
|
ca5774ed40
|
Try new LUT delays
|
2019-05-24 20:39:55 -07:00 |
Eddie Hung
|
60af2ca94d
|
Transpose CARRY4 delays
|
2019-05-24 14:09:15 -07:00 |
Eddie Hung
|
52e9036d39
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-05-23 13:38:04 -07:00 |
Eddie Hung
|
99a3fee8f4
|
Add "min bits" and "min wports" to xilinx dram rules
|
2019-05-23 11:32:28 -07:00 |
Eddie Hung
|
ae89e6ab26
|
Add whitebox support to DRAM
|
2019-05-23 08:58:57 -07:00 |
Eddie Hung
|
4f44e3399b
|
shift register inference before mux
|
2019-05-22 02:36:28 -07:00 |
Eddie Hung
|
9b1078b9bd
|
Fix/workaround symptom unveiled by #1023
|
2019-05-21 18:50:02 -07:00 |
Eddie Hung
|
ee8435b820
|
Instead of MUXCY/XORCY use CARRY4 (with timing)
|
2019-05-21 16:19:45 -07:00 |
Eddie Hung
|
36a219063a
|
Modify LUT area cost to be same as old abc
|
2019-05-21 14:31:19 -07:00 |
Eddie Hung
|
fb09c6219b
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-05-21 14:21:00 -07:00 |
Clifford Wolf
|
04ef222cfb
|
Add "stat -tech xilinx"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-05-11 09:24:52 +02:00 |
Clifford Wolf
|
09467bb9a3
|
Add "synth_xilinx -arch"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-05-07 15:04:36 +02:00 |
Eddie Hung
|
c2e29ab809
|
Rename cells_map.v to prevent clash with ff_map.v
|
2019-05-03 14:40:32 -07:00 |
Eddie Hung
|
283e33ba5a
|
Trim off leading 1'bx in A
|
2019-05-02 16:02:37 -07:00 |
Eddie Hung
|
fc72f07efd
|
Add don't care optimisation
|
2019-05-02 15:01:37 -07:00 |
Eddie Hung
|
d80445e049
|
Use new peepopt from #969
|
2019-05-02 11:35:57 -07:00 |
Eddie Hung
|
95867109ea
|
Revert to pre-muxcover approach
|
2019-05-02 11:25:10 -07:00 |
Eddie Hung
|
d05ac7257e
|
Missing help_mode
|
2019-05-02 11:14:28 -07:00 |
Eddie Hung
|
3b5e8c86a4
|
Fix -nocarry
|
2019-05-02 11:00:49 -07:00 |
Eddie Hung
|
5cd19b52da
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-05-02 10:44:59 -07:00 |
Eddie Hung
|
d394b9301b
|
Back to passing all xc7srl tests!
|
2019-05-01 18:23:21 -07:00 |
Eddie Hung
|
31ff0d8ef5
|
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
|
2019-05-01 18:09:38 -07:00 |
Marcin Kościelnicki
|
98e5a625c4
|
synth_xilinx: Add -nocarry and -nomux options.
|
2019-04-30 12:54:21 +02:00 |
Eddie Hung
|
e97178a888
|
WIP
|
2019-04-28 12:51:00 -07:00 |
Eddie Hung
|
af840bbc63
|
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
|
2019-04-28 12:36:04 -07:00 |
Eddie Hung
|
4aca928033
|
Fix spacing
|
2019-04-26 19:46:34 -07:00 |
Eddie Hung
|
d855683917
|
Revert synth_xilinx 'fine' label more to how it used to be...
|
2019-04-26 16:53:16 -07:00 |
Eddie Hung
|
ccc283737d
|
Apparently, this reduces number of MUXCY/XORCY
|
2019-04-26 16:28:48 -07:00 |
Eddie Hung
|
e31e21766d
|
Try a different approach with 'muxcover'
|
2019-04-26 16:09:54 -07:00 |
Eddie Hung
|
76b7c5d4cc
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-04-26 15:35:55 -07:00 |
Eddie Hung
|
ea0e0722bb
|
Where did this check come from!?!
|
2019-04-26 15:35:34 -07:00 |
Eddie Hung
|
6b9ca7cd6d
|
Remove split_shiftx call
|
2019-04-26 15:32:58 -07:00 |
Eddie Hung
|
8469d9fe9f
|
Missing newline
|
2019-04-26 14:51:37 -07:00 |
Eddie Hung
|
727eec04c5
|
Refactor synth_xilinx to auto-generate doc
|
2019-04-26 14:32:18 -07:00 |
Eddie Hung
|
f14d7f0df6
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Cleanup superseded
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2019-04-25 19:43:41 -07:00 |
Eddie Hung
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019c48b508
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bitblast_shiftx -> split_shiftx
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2019-04-25 19:38:35 -07:00 |
Eddie Hung
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feff976454
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synth_xilinx to call bitblast_shiftx
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2019-04-25 17:11:18 -07:00 |
Eddie Hung
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f96d82a5f1
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Add -nocarry option to synth_xilinx
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2019-04-24 16:46:41 -07:00 |
Eddie Hung
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0bd2bfa737
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-22 18:15:28 -07:00 |