Eddie Hung
0acc51c3d8
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
2019-10-04 17:35:43 -07:00
Eddie Hung
d4212d128b
Use read_args for read_verilog
2019-10-04 17:27:05 -07:00
Eddie Hung
9c23811839
Remove DSP48E1 from *_cells_xtra.v
2019-10-04 17:26:42 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
655f1b2ac5
English
2019-10-03 10:11:25 -07:00
Eddie Hung
5299884f04
More fixes
2019-10-01 13:41:08 -07:00
Eddie Hung
03ebe43e3e
Escape Verilog identifiers for legality outside of Yosys
2019-10-01 13:05:56 -07:00
Eddie Hung
e529872b01
Remove need for $currQ port connection
2019-09-30 16:33:40 -07:00
Eddie Hung
5e9ae90cbb
Add explanation to abc_map.v
2019-09-30 15:39:24 -07:00
Eddie Hung
8684b58bed
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 12:29:35 -07:00
Eddie Hung
5b5756b91e
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
Marcin Kościelnicki
4535f2c694
synth_xilinx: Support latches, remove used-up FF init values.
...
Fixes #1387 .
2019-09-30 12:52:43 +02:00
Eddie Hung
f6203e6bd6
Missing endmodule
2019-09-29 21:55:53 -07:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
...
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
18ebb86edb
FDCE_1 does not have IS_CLR_INVERTED
2019-09-29 11:25:34 -07:00
Eddie Hung
f3e150d9a5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 09:21:51 -07:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
c372e7baf9
Fix box name
2019-09-27 18:49:45 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Eddie Hung
b3d8a60cbd
Re-order
2019-09-27 14:32:07 -07:00
Eddie Hung
143f82def2
Missing an '&'
2019-09-26 11:13:08 -07:00
Eddie Hung
033aefc0f4
Typo
2019-09-26 10:34:14 -07:00
Eddie Hung
781dda6175
select once
2019-09-26 10:15:05 -07:00
Eddie Hung
27e5bf5aad
Stop trying to be too smart by prematurely optimising
2019-09-26 09:57:11 -07:00
Eddie Hung
53ea5daa42
Call 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 14:04:36 -07:00
Eddie Hung
93363c94a2
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-25 10:33:16 -07:00
Eddie Hung
b41d2fb4e4
Add (* techmap_autopurge *) to abc_unmap.v too
2019-09-23 22:02:22 -07:00
Eddie Hung
11ac37733d
Add techmap_autopurge to outputs in abc_map.v too
2019-09-23 21:56:28 -07:00
Eddie Hung
27167848f4
Revert "Add a xilinx_finalise pass"
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This reverts commit 23d90e0439
.
2019-09-23 19:52:55 -07:00
Eddie Hung
0f53893104
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
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This reverts commit 67c2db3486
.
2019-09-23 19:52:55 -07:00
Eddie Hung
29db96fa1f
Revert "Vivado does not like zero width port connections"
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This reverts commit 895e2befa7
.
2019-09-23 19:52:54 -07:00
Eddie Hung
895e2befa7
Vivado does not like zero width port connections
2019-09-23 19:04:07 -07:00
Eddie Hung
67c2db3486
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
2019-09-23 18:56:18 -07:00
Eddie Hung
23d90e0439
Add a xilinx_finalise pass
2019-09-23 18:56:02 -07:00
Eddie Hung
4401e5f142
Grammar
2019-09-20 14:24:31 -07:00
Eddie Hung
289cf688b7
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
2019-09-20 09:02:29 -07:00
Eddie Hung
691686f92c
Tidy up, fix undriven
2019-09-19 20:04:52 -07:00
Eddie Hung
1602516a8b
$__ABC_REG to have WIDTH parameter
2019-09-19 19:37:45 -07:00
Eddie Hung
e09f80479e
Fix DSP48E1 timing by breaking P path if MREG or PREG
2019-09-19 18:59:28 -07:00
Eddie Hung
362a803779
Revert "Different approach to timing"
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This reverts commit 41256f48a5
.
2019-09-19 18:33:38 -07:00
Eddie Hung
41256f48a5
Different approach to timing
2019-09-19 18:33:29 -07:00
Eddie Hung
5ca25b0c59
Suppress $anyseq warnings
2019-09-19 16:27:14 -07:00
Eddie Hung
595fb611a5
Use (* techmap_autopurge *) to suppress techmap warnings
2019-09-19 15:58:01 -07:00
Eddie Hung
c15a35db84
D is 25 bits not 24 bits wide
2019-09-19 15:55:49 -07:00
Eddie Hung
b88f0f6450
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
2019-09-19 15:47:41 -07:00
Eddie Hung
95db2489bd
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
2019-09-19 14:58:06 -07:00
Marcin Kościelnicki
13fa873f11
Use extractinv for synth_xilinx -ise
2019-09-19 04:02:48 +02:00
Eddie Hung
fd3b033903
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:23:22 -07:00
Eddie Hung
25e0f0c376
Fix copy-paste
2019-09-18 12:19:16 -07:00
Eddie Hung
b77cf6ba48
Mis-spell
2019-09-18 11:12:46 -07:00
Eddie Hung
e992dbf2c5
Add pattern detection support for DSP48E1 model, check against vendor
2019-09-18 10:45:04 -07:00
Marcin Kościelnicki
09ac36da60
xilinx: Make blackbox library family-dependent.
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Fixes #1246 .
2019-09-15 13:37:24 +02:00
Eddie Hung
681be20ca2
Add `undef DSP48E1_INST
2019-09-13 17:07:18 -07:00
Eddie Hung
61877e1370
Fix D -> P{,COUT} delay
2019-09-13 13:32:55 -07:00
Eddie Hung
d0b202c58d
Add no MULT no DPORT config
2019-09-13 12:05:14 -07:00
Eddie Hung
247a63f55d
Add support for MULT and DPORT
2019-09-13 11:45:55 -07:00
Eddie Hung
e235dd0785
Refine diagram
2019-09-13 09:34:40 -07:00
Eddie Hung
734034a872
Add an ASCII drawing
2019-09-12 18:13:46 -07:00
Eddie Hung
c52863f147
Finish explanation
2019-09-12 18:01:49 -07:00
Eddie Hung
aaeaab4ac0
Rename to techmap_guard
2019-09-12 17:45:02 -07:00
Eddie Hung
6bb8e6a726
Initial DSP48E1 box support
2019-09-12 17:11:01 -07:00
Eddie Hung
3a39073302
Set more ports explicitly
2019-09-12 17:10:43 -07:00
Eddie Hung
0ebbecf833
Missing space
2019-09-11 13:06:59 -07:00
Eddie Hung
feb3fa65a3
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-11 00:01:31 -07:00
Eddie Hung
5c1271c51c
Move "(skip if -nodsp)" message to label
2019-09-10 15:26:56 -07:00
Eddie Hung
76eedee089
Really get rid of 'opt_expr -fine' by being explicit
2019-09-10 14:26:12 -07:00
Eddie Hung
c460d10e60
Remove wreduce call
2019-09-10 14:17:35 -07:00
Eddie Hung
f3a55d3f06
Add comment for why opt_expr is necessary
2019-09-10 14:11:56 -07:00
Eddie Hung
8514e7c32e
Revert "Remove "opt_expr -fine" call"
...
This reverts commit bfda921d03
.
2019-09-10 14:09:21 -07:00
Eddie Hung
d3fb308181
Rename label to map_dsp
2019-09-10 13:18:10 -07:00
Eddie Hung
bfda921d03
Remove "opt_expr -fine" call
2019-09-10 13:17:47 -07:00
Eddie Hung
a7e6032287
Set USE_MULT and USE_SIMD
2019-09-09 20:56:29 -07:00
Marcin Kościelnicki
fda94311ee
synth_xilinx: Support init values on Spartan 6 flip-flops properly.
2019-09-07 16:30:43 +02:00
Eddie Hung
e742478e1d
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
Eddie Hung
aa1491add3
Resolve TODO with pin assignments for SRL*
2019-09-04 15:47:36 -07:00
Eddie Hung
3459d28349
Add comments
2019-09-02 12:22:15 -07:00
Eddie Hung
f33abd4eab
Remove trailing space
2019-08-30 16:44:11 -07:00
Eddie Hung
723815b384
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 13:26:19 -07:00
Eddie Hung
295c18bd6b
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-30 09:50:20 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
David Shah
6919c0f9b0
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
Eddie Hung
1b08f861b6
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Eddie Hung
9314a0a42e
Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
2019-08-28 10:51:39 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
Marcin Kościelnicki
d361f5ab79
xilinx: Add SRLC16E primitive.
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Fixes #1331 .
2019-08-27 20:27:12 +02:00
Eddie Hung
1ba09c4ab7
Merge branch 'master' into eddie/xilinx_srl
2019-08-26 13:56:31 -07:00
Eddie Hung
a098205479
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 13:25:17 -07:00
Eddie Hung
d7051b90de
Add undocumented feature
2019-08-23 16:41:32 -07:00
Eddie Hung
08139aa53a
xilinx_srl now copes with word-level flops $dff{,e}
2019-08-23 12:22:46 -07:00
Eddie Hung
78b7d8f531
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-23 11:32:44 -07:00
Eddie Hung
e658d472c8
Put attributes above port
2019-08-23 11:31:20 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
20f4d191b5
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 11:24:19 -07:00
Eddie Hung
509c353fe9
Forgot one
2019-08-23 11:23:50 -07:00
Eddie Hung
0d0ad15898
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 11:23:31 -07:00
Eddie Hung
a270af00cc
Put abc_* attributes above port
2019-08-23 11:21:44 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Eddie Hung
15188033da
Add variable length support to xilinx_srl
2019-08-21 17:34:40 -07:00
Eddie Hung
edec73fec1
abc9 to perform new 'map_ffs' before 'map_luts'
2019-08-21 15:37:55 -07:00
Eddie Hung
5ce0c31d0e
Add init support
2019-08-21 13:05:10 -07:00
Eddie Hung
c7af71ecde
Use semicolon
2019-08-21 11:47:17 -07:00
Eddie Hung
5d0f6cbd54
techmap before read
2019-08-21 11:47:06 -07:00
Eddie Hung
584c680691
Add abc_arrival to SRL*
2019-08-21 11:27:42 -07:00
Eddie Hung
b7a48e3e0f
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-20 20:18:17 -07:00
Eddie Hung
64d62710de
Oops
2019-08-20 20:07:38 -07:00
Eddie Hung
c26c556384
xilinx to use abc_map.v with -max_iter 1
2019-08-20 19:47:11 -07:00
Eddie Hung
343039496b
Add reference to FD* timing
2019-08-20 18:22:58 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
...
This reverts commit 091bf4a18b
.
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
bbab608691
Remove SRL* delays from cells_sim.v
2019-08-20 18:14:40 -07:00
Eddie Hung
aa2d3af631
LUTMUX -> LUTMUX6
2019-08-20 18:08:07 -07:00
Eddie Hung
30a379b5b6
Cleanup techmap in map_luts
2019-08-20 17:59:31 -07:00
Eddie Hung
3b52d6e29c
Move `techmap abc_map.v` into map_luts
2019-08-20 17:55:12 -07:00
Eddie Hung
54284aaa98
Remove delays from abc_map.v
2019-08-20 17:52:27 -07:00
Eddie Hung
96f00e9147
Typo
2019-08-20 17:51:50 -07:00
Eddie Hung
8f666ebac1
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 17:36:14 -07:00
Eddie Hung
e273ed5275
Wrap SRL{16,32} too
2019-08-20 15:09:38 -07:00
Eddie Hung
808f07630f
Wrap LUTRAMs in order to capture comb/seq behaviour
2019-08-20 14:49:11 -07:00
Eddie Hung
0079e9b4a6
Add LUTRAM delays
2019-08-20 13:53:38 -07:00
Eddie Hung
8d0cffaf20
Remove mapping rules
2019-08-20 13:11:39 -07:00
Eddie Hung
33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
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[WIP] synth xilinx renaming, as per #1184
2019-08-20 12:55:26 -07:00
Eddie Hung
5eda5fc7eb
Remove -icells
2019-08-20 12:41:11 -07:00
Eddie Hung
be9e4f1b67
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Eddie Hung
d9fe4cccbf
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
2019-08-20 11:57:52 -07:00
Eddie Hung
526e081342
Add arrival times for SRL outputs
2019-08-19 15:15:43 -07:00
Eddie Hung
b71212ddea
Add BRAM arrival times
2019-08-19 12:46:35 -07:00
Eddie Hung
2f86366087
Add reference to source of Tclktoq timing
2019-08-19 12:39:22 -07:00
Eddie Hung
d02ef8c73f
Add 'abc_arrival' attribute for flop outputs
2019-08-19 11:32:18 -07:00
Eddie Hung
f25837f8e8
Update box timings
2019-08-19 11:31:40 -07:00
Eddie Hung
ba2261e21a
Move from cell attr to module attr
2019-08-19 11:18:33 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Eddie Hung
e301440a0b
Use attributes instead of params
2019-08-19 09:51:49 -07:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
562c9e3624
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
2019-08-16 15:40:53 -07:00
Eddie Hung
261daffd9d
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-15 12:19:47 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Eddie Hung
ed4b2834ef
Add assign PCOUT = P to DSP48E1
2019-08-13 12:19:26 -07:00
Marcin Kościelnicki
49765ec19e
minor review fixes
2019-08-13 18:05:49 +00:00
Eddie Hung
2a1b98d478
Add DSP_A_MAXWIDTH_PARTIAL, refactor
2019-08-13 10:21:24 -07:00
David Shah
edff79a25a
xilinx: Rework labels for faster Verilator testing
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-13 10:29:42 +01:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
...
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
f890cfb63b
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 11:32:10 -07:00
Eddie Hung
0b5b56c1ec
Pack partial-product adder DSP48E1 packing
2019-08-09 15:19:33 -07:00
Eddie Hung
1f722b3500
Remove signed from ports in +/xilinx/dsp_map.v
2019-08-08 16:33:20 -07:00