riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,903 Commits 87 Branches 48 Tags 38 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
whitequark c285880684 fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00