riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,903 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
Marcelina Kościelnicka f61f2a4078 gowin: Fix LUT RAM inference, add more models. 2022-02-09 09:04:34 +01:00
Eddie Hung caab66111e Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00