riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,334 Commits 89 Branches 49 Tags 38 MiB
Commit Graph

9334 Commits

Author SHA1 Message Date
Eddie Hung 3be7784d0e xaiger: remove some unnecessary operations ... 
... since they can not be triggered by (* keep *) anymore
(but could still be triggered by (* abc9_scc *) !?!)
 2020-03-06 10:51:47 -08:00
Eddie Hung 7a89ed1fa2 Bump ABCREV to receive fix for #1675 2020-03-06 10:32:48 -08:00
Eddie Hung 80dcc8a0d1 abc9: for sccs, create a new wire instead of using entirety of existing 2020-03-06 10:30:07 -08:00
Eddie Hung 91a7a74ac4 abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling 2020-03-06 10:20:30 -08:00
Eddie Hung 2335c59e5b abc: add abc.debug scratchpad option 2020-03-06 10:09:01 -08:00
N. Engelhardt 8a39a580e1 remove unused parameters 2020-03-06 16:45:36 +01:00
Miodrag Milanović bfeba9ad11
Merge pull request #1742 from nakengelhardt/rpc-test-again 
More rpc test fixes
 2020-03-06 16:06:54 +01:00
N. Engelhardt 88494e81f5 rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors 2020-03-06 15:29:01 +01:00
Eddie Hung 8b074cc473
Merge pull request #1739 from YosysHQ/eddie/issue1738 
ice40: fix specify for -device {lp,u}
 2020-03-05 09:41:54 -08:00
Eddie Hung 69f1555058 ice40: fix specify for ICE40_{LP,U} 2020-03-05 08:11:49 -08:00
Eddie Hung 3c2e910bb3 tests: extend tests/arch/run-tests.sh for defines 2020-03-05 08:08:32 -08:00
Eddie Hung 0930c00f03 ice40: fix implicit signal in specify, also clamp negative times to 0 2020-03-04 15:28:17 -08:00
Eddie Hung 6eb528277e
Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1 
xilinx: cleanup DSP48E1 handling for abc9
 2020-03-04 13:37:09 -08:00
Eddie Hung 7b543fdb0c xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
Eddie Hung 512596760b xilinx: cleanup DSP48E1 handling for abc9 2020-03-04 11:31:12 -08:00
Eddie Hung f65fc845e5 xilinx: improve specify for DSP48E1 2020-03-04 11:31:12 -08:00
Eddie Hung 78d4fff69d xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v 2020-03-04 11:31:12 -08:00
David Shah 5cae9c6e16 deminout: Don't demote inouts with unused bits 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-04 18:44:38 +00:00
N. Engelhardt 0ec971444b
Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc 
Add -flowmap option to `synth{,_ice40}`
 2020-03-03 19:15:41 +01:00
Claire Wolf d59da5a4e4 Fix bison warning for "pure-parser" option 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-03 08:41:55 -08:00
Claire Wolf b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Claire Wolf 91892465e1
Merge pull request #1681 from YosysHQ/eddie/fix1663 
verilog: instead of modifying localparam size, extend init constant expr
 2020-03-03 08:34:31 -08:00
Claire Wolf 879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po 
submod: several bugfixes
 2020-03-03 08:19:06 -08:00
Marcelina Kościelnicka 968956badb
iopadmap: Look harder for already-present buffers. (#1731) 
iopadmap: Look harder for already-present buffers.

Fixes #1720.
 2020-03-02 21:40:09 +01:00
Eddie Hung 4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify 
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
 2020-03-02 12:32:27 -08:00
N. Engelhardt b1e248b0e6
Merge pull request #1729 from rqou/coolrunner2 
coolrunner2 buffer cell insertion fixes
 2020-03-02 12:31:05 +01:00
R. Ou 7932672fc2 coolrunner2: Attempt to give wires/cells more meaningful names 2020-03-02 01:40:57 -08:00
R. Ou b9c98e0100 coolrunner2: Fix invalid multiple fanouts of XOR/OR gates 
In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:

module top(input a, input b, input clk_, output reg o, output o2);

wire clk;

BUFG bufg0 (
    .I(clk_),
    .O(clk),
);

always @(posedge clk)
    o = a ^ b;
assign o2 = a ^ b;

endmodule
 2020-03-02 01:07:15 -08:00
R. Ou a618004897 coolrunner2: Fix packed register+input buffer insertion 
The register will be packed with the input buffer if and only if the
input buffer doesn't have any other loads.
 2020-03-02 00:32:57 -08:00
R. Ou a6aeee4e1a coolrunner2: Insert many more required feedthrough cells 2020-03-01 16:56:21 -08:00
Eddie Hung 69c2d3848a
Merge pull request #1727 from YosysHQ/eddie/fix_write_smt2 
ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
 2020-02-29 08:15:24 -08:00
Eddie Hung de3e5fcdc6 ystests: fix write_smt2_write_smt2_cyclic_dependency_fail 2020-02-28 12:33:55 -08:00
Eddie Hung b741954461
Merge pull request #1726 from YosysHQ/eddie/fix1710 
ast: fixes #1710; do not generate RTLIL for unreachable ternary branch
 2020-02-28 10:39:03 -08:00
Dan Ravensloft d7987fec12 Add -flowmap to synth and synth_ice40 2020-02-28 14:29:57 +00:00
Eddie Hung 5bba9c3640 ast: fixes #1710; do not generate RTLIL for unreachable ternary 2020-02-27 16:55:55 -08:00
Eddie Hung 825b96fdcf Comment out log() 2020-02-27 16:53:49 -08:00
Eddie Hung 090e54569a Remove RAMB{18,36}E1 from cells_xtra.py 2020-02-27 10:33:04 -08:00
Eddie Hung 0f4c1906bb Small fixes 2020-02-27 10:29:53 -08:00
Eddie Hung 78929e8c3d Fixes for older compilers 2020-02-27 10:17:29 -08:00
Eddie Hung a179d918ec Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" 
This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
 2020-02-27 10:17:29 -08:00
Eddie Hung e79376d6cb ast: quiet down when deriving blackbox modules 2020-02-27 10:17:29 -08:00
Eddie Hung 88d5997c80 abc9_ops: suppress -prep_box warning for abc9_flop 2020-02-27 10:17:29 -08:00
Eddie Hung 376319dc8d xilinx: Update RAMB* specify entries 2020-02-27 10:17:29 -08:00
Eddie Hung 6bd9550100 ice40: add delays to SB_CARRY 2020-02-27 10:17:29 -08:00
Eddie Hung 3b74e0fa45 xilinx: add delays to INV 2020-02-27 10:17:29 -08:00
Eddie Hung 6bb3d9f9c0 Make TimingInfo::TimingInfo(SigBit) constructor explicit 2020-02-27 10:17:29 -08:00
Eddie Hung 9dcf204dec TimingInfo: index by (port_name,offset) 2020-02-27 10:17:29 -08:00
Eddie Hung 7c3b4b80ea Fix spacing 2020-02-27 10:17:29 -08:00
Eddie Hung aa969f8778 More +/ice40/cells_sim.v fixes 2020-02-27 10:17:29 -08:00
Eddie Hung f858219c4e Cleanup tests 2020-02-27 10:17:29 -08:00