Eddie Hung
6bd9550100
ice40: add delays to SB_CARRY
2020-02-27 10:17:29 -08:00
Eddie Hung
3b74e0fa45
xilinx: add delays to INV
2020-02-27 10:17:29 -08:00
Eddie Hung
aa969f8778
More +/ice40/cells_sim.v fixes
2020-02-27 10:17:29 -08:00
Eddie Hung
b0ffd9cd8b
Make +/xilinx/cells_sim.v legal
2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
Eddie Hung
3ea5506f81
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
7d86aceee3
Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy
2020-02-27 10:17:29 -08:00
Eddie Hung
3728ef1765
ice40: fix specify for inverted clocks
2020-02-27 10:17:29 -08:00
Eddie Hung
aac309626b
Fix tests by gating some specify constructs from iverilog
2020-02-27 10:17:29 -08:00
Eddie Hung
e22fee6cdd
abc9_ops: ignore (* abc9_flop *) if not '-dff'
2020-02-27 10:17:29 -08:00
Eddie Hung
a76520112d
ice40: specify fixes
2020-02-27 10:17:29 -08:00
Eddie Hung
fb60d82971
ice40: move over to specify blocks for -abc9
2020-02-27 10:17:29 -08:00
Eddie Hung
a85c55113f
synth_ecp5: use +/abc9_model.v
2020-02-27 10:17:29 -08:00
Eddie Hung
8408c13405
Update xilinx for ABC9
2020-02-27 10:17:29 -08:00
Eddie Hung
ac24a23e31
Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
2020-02-27 10:17:29 -08:00
Eddie Hung
d2284715fa
ecp5: remove small LUT entries
2020-02-27 10:17:29 -08:00
Eddie Hung
ccc84f8923
Fix commented out specify statement
2020-02-27 10:17:29 -08:00
Eddie Hung
12d70ca8fb
xilinx: improve specify functionality
2020-02-27 10:17:29 -08:00
Eddie Hung
46a89d7264
ecp5: deprecate abc9_{arrival,required} and *.{lut,box}
2020-02-27 10:17:29 -08:00
Eddie Hung
577545488a
xilinx: use specify blocks in place of abc9_{arrival,required}
2020-02-27 10:17:29 -08:00
Eddie Hung
0e7c55e2a7
Auto-generate .box/.lut files from specify blocks
2020-02-27 10:17:29 -08:00
Eddie Hung
74f49b1f55
abc9_ops: -prep_box, to be called once
2020-02-27 10:17:29 -08:00
Eddie Hung
5643c1b8c5
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
2020-02-27 10:17:29 -08:00
Claire Wolf
ab8826ae36
Merge pull request #1709 from rqou/coolrunner2_counter
...
Improve CoolRunner-II optimization by using extract_counter pass
2020-02-27 19:05:56 +01:00
Claire Wolf
47228feb77
Merge pull request #1708 from rqou/coolrunner2-buf-fix
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coolrunner2: Separate and improve buffer cell insertion pass
2020-02-27 19:03:59 +01:00
Piotr Binkowski
62ab100c61
xilinx: mark IOBUFDSE3 IOB pin as external
2020-02-27 13:15:57 +01:00
Marcus Comstedt
48a9b4f616
ecp5: Add missing parameter to \$__ECP5_PDPW16KD
2020-02-22 15:51:25 +01:00
R. Ou
13d0ff4a5f
coolrunner2: Use extract_counter to optimize counters
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This tends to make much more efficient pterm usage compared to just
throwing the problem at ABC
2020-02-17 03:09:40 -08:00
R. Ou
6a0682f5a0
coolrunner2: Separate and improve buffer cell insertion pass
...
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
2020-02-16 20:25:46 -08:00
Miodrag Milanovic
cd5c177739
Remove executable flag from files
2020-02-15 10:36:44 +01:00
Eddie Hung
00d41905df
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
2020-02-13 12:33:58 -08:00
Eddie Hung
c244b27b6d
abc9: cleanup
2020-02-10 10:17:23 -08:00
Eddie Hung
2e8d6ec0b0
Remove unnecessary comma
2020-02-07 12:45:07 -08:00
Eddie Hung
affae35847
techmap: fix shiftx2mux decomposition
2020-02-07 11:02:48 -08:00
Marcin Kościelnicki
89adef352f
xilinx: Add support for LUT RAM on LUT4-based devices.
...
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d
xilinx: Initial support for LUT4 devices.
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Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
2020-02-07 09:03:22 +01:00
Eddie Hung
1f54b0008f
Merge pull request #1685 from dh73/gowin
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Removing cells_sim from GoWin bram techmap
2020-02-06 20:59:21 -08:00
Marcin Kościelnicki
30854b9c7f
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
Marcin Kościelnicki
95c46ccc55
xilinx: Add support for Spartan 3A DSP block RAMs.
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Part of #1550
2020-02-07 01:00:29 +01:00
Eddie Hung
1784d25f53
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map
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Fix/cleanup +/xilinx/arith_map.v
2020-02-06 13:51:23 -08:00
Diego H
87883f6d88
Removing cells_sim.v from bram techmap pass
2020-02-06 14:38:29 -06:00
Eddie Hung
d625e399cb
Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
2020-02-06 11:25:07 -08:00
Eddie Hung
5ecbc6c7b2
Fix/cleanup +/xilinx/arith_map.v
2020-02-06 11:00:04 -08:00
whitequark
081d9318bc
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
...
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
whitequark
3f4460a186
ice40: match memory inference attribute values case insensitive.
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LSE/Synplify use case insensitive matching.
2020-02-06 14:58:20 +00:00
whitequark
fc28bf55aa
ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
...
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 14:58:20 +00:00
Eddie Hung
0b0148399c
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
Eddie Hung
4c1d3a126d
shiftx2mux: fix select out of bounds
2020-02-05 16:41:09 -08:00
Eddie Hung
b6a1f627b5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
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abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Marcin Kościelnicki
b44d0e041f
xilinx: use RAM32M/RAM64M for memories with two read ports
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This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
2020-02-02 14:34:21 +01:00
Claire Wolf
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental
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Add log_experimental() and experimental() API and "yosys -x"
2020-01-29 15:25:03 +01:00
Eddie Hung
c5971cb16c
synth_xilinx: cleanup help
2020-01-28 17:48:43 -08:00
Eddie Hung
0fd64aab25
synth_xilinx: fix help when no active_design; fixes #1664
2020-01-28 17:41:57 -08:00
Marcin Kościelnicki
7e0e42f907
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
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Unpermute LUT ordering for ice40/ecp5/xilinx
2020-01-28 11:55:51 -08:00
Eddie Hung
245b8c4ab6
Fix unresolved conflict from #1573
2020-01-28 10:17:47 -08:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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synth_xilinx: error out if tristate without '-iopad'
2020-01-28 17:24:54 +01:00
Eddie Hung
e18aeda7ed
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
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Just like Verilog...
2020-01-27 14:02:13 -08:00
Eddie Hung
cfb0366a18
Import tests from #1628
2020-01-27 13:56:16 -08:00
Eddie Hung
ce6a690d27
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
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Now done in read_aiger
2020-01-27 13:30:27 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
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Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung
f2576c096c
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
2020-01-27 12:29:28 -08:00
Eddie Hung
af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-27 09:54:04 -08:00
Claire Wolf
cef607c8b7
Add log_experimental() and experimental() API and "yosys -x"
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 18:27:47 +01:00
Eddie Hung
81e6b040a4
ice40: add SB_SPRAM256KA arrival time
2020-01-24 12:17:09 -08:00
Eddie Hung
b178761551
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
Eddie Hung
7858cf20a9
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
2020-01-23 19:02:27 -08:00
Eddie Hung
da134701cd
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
2020-01-22 14:22:03 -08:00
Eddie Hung
72e4540ca9
Explicitly create separate $mux cells
2020-01-21 16:49:34 -08:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Eddie Hung
152dfd3dd4
Fix tests -- when Y_WIDTH is non-pow-2
2020-01-21 15:19:41 -08:00
Eddie Hung
8d1b736c4f
Move from +/shiftx2mux.v into +/techmap.v; cleanup
2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
2020-01-21 15:19:41 -08:00
Eddie Hung
b7be6cfd65
Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map
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Cleanup +/xilinx/arith_map.v
2020-01-18 09:11:52 -08:00
David Shah
a4cfd1237f
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning
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ice40: Demote conflicting FF init values to a warning
2020-01-18 09:47:17 +00:00
Eddie Hung
78ffd5d193
synth_ice40: call wreduce before mul2dsp
2020-01-17 15:41:55 -08:00
Eddie Hung
5c589244df
Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623
2020-01-17 12:02:46 -08:00
Eddie Hung
1e6d56dca1
+/xilinx/arith_map.v fix $lcu rule
2020-01-17 11:28:37 -08:00
Eddie Hung
b0605128b6
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-15 16:42:27 -08:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
5a63c19747
abc9_ops: -write_box is empty, output a dummy box to prevent ABC error
2020-01-15 13:14:48 -08:00
Miodrag Milanović
abba1541bc
Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W
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synth_xilinx: fix default W value for non-xc7
2020-01-15 08:47:16 +01:00
Eddie Hung
0e4285ca0d
abc9_ops: generate flop box ids, add abc9_required to FD* cells
2020-01-14 15:05:49 -08:00
Eddie Hung
915e7dde73
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 12:57:56 -08:00
Eddie Hung
d21262ee04
Adding (* techmap_autopurge *) to FD* in abc9_map.v
2020-01-14 12:22:21 -08:00
Eddie Hung
36d1a2c60f
synth_xilinx: fix default W value for non-xc7
2020-01-14 11:34:40 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
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Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
Eddie Hung
ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad
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abc9: add some scripts/options into "scratchpad"
2020-01-13 09:04:20 -08:00
Eddie Hung
f9aae90e7a
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-12 15:19:41 -08:00
Eddie Hung
c0b55deb0b
synth_ice40: -abc2 to always use `abc` even if `-abc9`
2020-01-12 11:26:05 -08:00
Eddie Hung
35e49fde4d
Another conflict
2020-01-11 18:57:25 -08:00
Eddie Hung
c063436eea
Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
2020-01-11 17:02:20 -08:00
Eddie Hung
28f814ee59
Add abc9_required to DSP48E1.{A,B,C,D,PCIN}
2020-01-10 17:12:31 -08:00
Eddie Hung
7d94e18100
synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro
2020-01-10 15:07:46 -08:00
Eddie Hung
475d983676
abc9_ops -prep_times: generate flop boxes from abc9_required attr
2020-01-10 14:49:52 -08:00
Eddie Hung
b2259a9201
Add abc9_ops -check, -prep_times, -write_box for required times
2020-01-10 11:45:41 -08:00
Miodrag Milanovic
992b507537
Use CARRY4 for abc1 as well, preventing issues with Vivado
2020-01-10 12:34:21 +01:00
Eddie Hung
57f6826e29
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-08 18:30:20 -08:00