whitequark
9bb839c613
Merge pull request #2626 from zachjs/param-no-default
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sv: support for parameters without default values
2021-03-07 05:48:03 -08:00
whitequark
72ae15c77c
Merge pull request #2632 from zachjs/width-limit
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verilog: impose limit on maximum expression width
2021-03-07 03:45:41 -08:00
Zachary Snow
b1a8e73a60
sv: fix some edge cases for unbased unsized literals
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- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
2021-03-06 15:20:34 -05:00
Marcelina Kościelnicka
d245e2bae5
proc_clean: Fix empty case removal conditions.
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Fixes #2639 .
2021-03-06 17:39:50 +01:00
Marcelina Kościelnicka
3d2aef0bde
Remove a few functions that, in fact, did not exist in the first place.
2021-03-06 01:19:49 +01:00
Dan Ravensloft
55e5bd4213
Replace assert in addModule with more useful error message
2021-03-06 00:10:28 +01:00
whitequark
9dd813374e
Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr
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cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
2021-03-05 05:30:19 -08:00
whitequark
06da2e0f18
Merge pull request #2634 from whitequark/cxxrtl-debug-wire-types
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cxxrtl: add pass debug flag to show assigned wire types
2021-03-05 04:57:22 -08:00
whitequark
b117f9bba8
Merge pull request #2633 from whitequark/cxxrtl-no-top
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cxxrtl: don't crash on empty designs
2021-03-05 04:14:07 -08:00
whitequark
14ce8bdaa6
cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
2021-03-05 12:09:02 +00:00
whitequark
8471808834
cxxrtl: add pass debug flag to show assigned wire types.
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Refs #2543 .
2021-03-05 11:58:59 +00:00
whitequark
a9a873a1d2
cxxrtl: don't crash on empty designs.
2021-03-05 11:05:19 +00:00
Zachary Snow
c18ddbcd82
verilog: impose limit on maximum expression width
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Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
2021-03-04 15:20:52 -05:00
Claire Xen
7d2097b005
Update command-reference-manual.tex
2021-03-04 16:45:21 +01:00
Claire Xen
6c56c083f8
Update README
2021-03-04 16:43:30 +01:00
Zachary Snow
d738b2c127
sv: support for parameters without default values
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- Modules with a parameter without a default value will be automatically
deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
2021-03-02 10:43:53 -05:00
whitequark
375af199ef
Merge pull request #2620 from zachjs/port-int-types
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verilog: fix sizing of ports with int types in module headers
2021-03-01 22:46:07 -08:00
Zachary Snow
10a6bc9b81
verilog: fix sizing of ports with int types in module headers
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Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
2021-03-01 13:39:05 -05:00
Marcelina Kościelnicka
0e0f84299a
Bump version
2021-03-01 19:33:05 +01:00
Zachary Snow
1ec5994100
verilog: fix handling of nested ifdef directives
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- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00
Zachary Snow
b6904a8e53
Set aside extraneous tests in simple_abc9 test suite
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New test cases on one branch may be automatically copied from simple/ to
simple_abc9/, causing failures when switching to another branch. This
updates the simple_abc9 script to set aside extraneous tests in a
non-destructive way.
2021-03-01 12:13:11 -05:00
Claire Xen
004b780b8a
Merge pull request #2523 from tomverbeure/define_synthesis
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Add -nosynthesis flag for read_verilog command
2021-03-01 18:00:48 +01:00
Claire Xen
527c681a2b
Merge pull request #2524 from bkbncn/patch-1
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Add boost-python3
2021-03-01 17:46:33 +01:00
whitequark
7b47dd0f88
Merge pull request #2617 from RobertBaruch/doc
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RTLIL Documentation: switch in process is optional
2021-03-01 08:10:32 -08:00
whitequark
ca5f5ffcd6
Merge pull request #2615 from zachjs/genrtlil-conflict
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genrtlil: improve name conflict error messaging
2021-03-01 08:10:19 -08:00
whitequark
0fb4224ebc
Merge pull request #2618 from zachjs/int-types
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sv: extended support for integer types
2021-02-28 20:29:44 -08:00
Zachary Snow
0f5b646ab8
sv: extended support for integer types
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- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
Robert Baruch
ca4b1afcb6
RTLIL Documentation: switch in process is optional
2021-02-27 09:58:03 -08:00
Claire Xen
d882b6fe3c
Update issue_template.md
2021-02-27 16:52:30 +01:00
Zachary Snow
bbff844acd
genrtlil: improve name conflict error messaging
2021-02-26 18:08:23 -05:00
Michael Singer
d56b76bd7c
Add tests for $countbits
2021-02-26 12:28:58 -05:00
Michael Singer
04b41ed04a
Implement $countones, $isunknown and $onehot{,0}
2021-02-26 12:28:58 -05:00
Michael Singer
8434ba5a3b
Implement $countbits function
2021-02-26 12:28:58 -05:00
Zachary Snow
22bed38540
Extend simplify() recursion warning
2021-02-26 12:11:23 -05:00
Marcelina Kościelnicka
5d0cc54f5c
Bump version
2021-02-26 00:24:33 +01:00
whitequark
58a5755187
Merge pull request #2554 from hzeller/master
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Fix digit-formatting calculation for small numbers.
2021-02-25 13:54:16 -08:00
Marcelina Kościelnicka
979347999f
btor, smt2, smv: Add a hint on how to deal with funny FF types.
2021-02-25 22:04:04 +01:00
Marcelina Kościelnicka
a651204efa
Fix handling of unique/unique0/priority cases in the frontend.
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Basically:
- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)
Fixes #2596 .
2021-02-25 21:53:58 +01:00
TimRudy
dcd9f0af23
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off ( #2566 )
2021-02-24 15:48:15 -05:00
whitequark
fffbf651df
Merge pull request #2607 from zachjs/logger-error-atexit
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Fix double-free on unmatched logger error pattern
2021-02-24 19:12:56 +00:00
Zachary Snow
5e439b6e3f
Fix double-free on unmatched logger error pattern
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When an expected logger error pattern is unmatched, the logger raises
another (hidden) error. Because of the previous ordering of actions,
`logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()`
twice, causing a double-free.
2021-02-23 20:49:21 -05:00
Marcelina Kościelnicka
b05b98521c
Add tests for some common techmap files.
2021-02-24 01:07:34 +01:00
Marcelina Kościelnicka
cde73428b0
Fix syntax error in adff2dff.v
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Fixes #2600 .
2021-02-24 01:07:34 +01:00
Marcelina Kościelnicka
f4f471f342
frontend: Make helper functions for printing locations.
2021-02-23 23:51:52 +01:00
whitequark
ad2960adb7
Merge pull request #2594 from zachjs/func-arg-width
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verilog: fix sizing of constant args for tasks/functions
2021-02-23 21:46:16 +00:00
Robert Baruch
4b31223e60
int -> bool
2021-02-23 17:52:43 +01:00
Robert Baruch
7c50b89b24
Adds is_wire to SigBit and SigChunk
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Useful for PYOSYS because Python can't easily check wire against NULL.
2021-02-23 17:52:43 +01:00
William D. Jones
ae07298a6b
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
2021-02-23 17:39:58 +01:00
William D. Jones
353ace5034
machxo2: Update tribuf test to reflect active-low OE.
2021-02-23 17:39:58 +01:00
William D. Jones
8f1a350f5e
machxo2: Add experimental status to help.
2021-02-23 17:39:58 +01:00