riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
11,030 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

11030 Commits

Author SHA1 Message Date
Marcelina Kościelnicka a4c04d1b90 ast: fix dump_vlog display of casex/casez 
The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.
 2021-01-29 16:28:15 +01:00
whitequark 708eb327a1
Merge pull request #2564 from whitequark/flatten-improve-error 
flatten: clarify confusing error message
 2021-01-29 02:55:51 +00:00
Yosys Bot ffa1cb836b Bump version 2021-01-29 00:10:05 +00:00
whitequark 74b0c38520
Merge pull request #2569 from zachjs/macro-arg-surrounding-spaces 
verilog: strip leading and trailing spaces in macro args
 2021-01-28 21:32:27 +00:00
Claire Xen d0d7a360ed
Merge pull request #2535 from Ravenslofty/scc-specify 
scc: Add -specify option to find loops in boxes
 2021-01-28 19:01:29 +01:00
Zachary Snow 27257a419f verilog: strip leading and trailing spaces in macro args 2021-01-28 11:26:35 -05:00
Yosys Bot 98afe2b758 Bump version 2021-01-27 00:10:04 +00:00
Marcelina Kościelnicka ea79e16bab xilinx_dffopt: Don't crash on missing IS_*_INVERTED. 
The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll.  Just assume false if the
parameter doesn't exist.

Fixes #2559.
 2021-01-27 00:32:00 +01:00
Marcelina Kościelnicka cd6f0732f3 xilinx: Add FDRSE_1, FDCPE_1. 2021-01-27 00:32:00 +01:00
whitequark a77fa6709b
Merge pull request #2563 from whitequark/cxxrtl-msvc 
cxxrtl: do not use `->template` for non-dependent names
 2021-01-26 21:55:12 +00:00
whitequark d73ffa07f2
Merge pull request #2544 from modwizcode/fix-clock 
CXXRTL: Fix sliced bits as clock inputs
 2021-01-26 21:18:06 +00:00
whitequark 2364820f50 flatten: clarify confusing error message. 2021-01-26 18:29:53 +00:00
whitequark 4b6e764c46 cxxrtl: do not use `->template` for non-dependent names. 
This breaks build on MSVC but not GCC/Clang.
 2021-01-26 18:09:53 +00:00
Dan Ravensloft 74dad5afe7 scc: Add -specify option to find loops in boxes 2021-01-26 16:23:08 +00:00
Yosys Bot 8eaeaa8434 Bump version 2021-01-26 00:10:05 +00:00
whitequark f200a8fe1c
Merge pull request #2549 from pgadfort/support-multiple-libs 
adding support for passing multiple liberty files to abc
 2021-01-25 10:36:14 +00:00
whitequark ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces 
verilog: allow spaces in macro arguments
 2021-01-25 10:36:07 +00:00
Yosys Bot 410ea42242 Bump version 2021-01-25 00:10:07 +00:00
Claire Xen 2257a9a721
Merge pull request #2558 from YosysHQ/dave/chandle-dpi 
dpi: Support for chandle type
 2021-01-24 02:45:08 +01:00
David Shah 09311b6581 dpi: Support for chandle type 
Signed-off-by: David Shah <dave@ds0.me>
 2021-01-23 22:24:31 +00:00
Yosys Bot 54294957ed Bump version 2021-01-22 00:10:05 +00:00
Henner Zeller 7d014902ec Fix digit-formatting calculation for small numbers. 
Calling log10() on zero causes a non-sensical value to be calculated. On some
compile options, I've observed yosys crashing with an illegal
instruction (SIGILL).

To make it safe, fix the calculation to do a range check; wrap it a
decimal_digits() function, and use it where the previous ceil(log10(n)) call
was used. As a side, it also improves readability.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2021-01-21 12:20:53 -08:00
Miodrag Milanović 1f88a3de74
Merge pull request #2553 from zachjs/rand-const-modifiers 
Allow combination of rand and const modifiers
 2021-01-21 16:56:19 +01:00
Zachary Snow 1096b969ef Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00
Yosys Bot 699a98b265 Bump version 2021-01-21 00:10:05 +00:00
Claire Xen b734f2c932
Merge pull request #2552 from YosysHQ/claire/yosyshq 
Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
 2021-01-21 00:54:45 +01:00
Claire Xenia Wolf acad7a6e40 Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-01-20 20:48:10 +01:00
Miodrag Milanović bfa353f154
Merge pull request #2536 from TobiasFaller/master 
Fixed missing goto statement in passes/techmap/abc.cc
 2021-01-20 20:42:02 +01:00
Miodrag Milanović 00f02e0589
Merge pull request #2551 from zachjs/wire-logic 
sv: fix support wire and var data type modifiers
 2021-01-20 18:31:49 +01:00
Zachary Snow 006c18fc11 sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00
Zachary Snow 4fadcc8f25 verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00
Yosys Bot 4762cc06c6 Bump version 2021-01-19 00:10:05 +00:00
Peter Gadfort 169234d6e9 adding support for passing multiple liberty files to abc 2021-01-18 16:47:49 -05:00
whitequark e991ceeef3
Merge pull request #2547 from zachjs/plugin-so-dsym 
Add plugin.so.dSYM to .gitignore
 2021-01-18 20:21:20 +00:00
whitequark 056c12eb6f
Merge pull request #2312 from antmicro/typedef-inout 
Add support for user types in IOs
 2021-01-18 20:20:52 +00:00
Zachary Snow 4c108b4419 Add plugin.so.dSYM to .gitignore 
This artifact is automatically generated by the builtin clang on macOS
when -g is used.
 2021-01-18 11:13:21 -07:00
Kamil Rakoczy d69ddf19da Add typedef input/output test 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-01-18 17:31:22 +01:00
Kamil Rakoczy 61501e3266 Fix input/output attributes when resolving typedef of wire 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-01-18 17:31:22 +01:00
Lukasz Dalek 09071afe15 Parse package user type in module port list 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-01-18 17:31:22 +01:00
Iris Johnson c8415884d1 Improves the previous commit with a more complete coverage of the cases 2021-01-15 13:59:20 -06:00
Yosys Bot 339848b954 Bump version 2021-01-15 00:10:05 +00:00
Iris Johnson 86607d0fdc Handle sliced bits as clock inputs (fixes #2542) 2021-01-14 16:36:21 -06:00
Marcelina Kościelnicka 01626e6746 opt_share: Fix X and CO signal width for shifted $alu in opt_share. 
These need to be the same length as actual Y, not visible part of Y.

Fixes #2538.
 2021-01-14 14:54:08 +01:00
Yosys Bot 7cd044bbc4 Bump version 2021-01-14 00:10:05 +00:00
Claire Xen 0927675147
Merge pull request #2537 from pepijndevos/spice 
Add buffer option to spice backend
 2021-01-13 19:08:25 +01:00
Pepijn de Vos e789a00557 add buffer option to spice backend 2021-01-13 17:24:28 +01:00
Tobias Faller 760a2c1343 Fixed missing goto statement in passes/techmap/abc.cc 2021-01-12 16:17:51 +01:00
Yosys Bot b0004911ca Bump version 2021-01-05 00:10:05 +00:00
whitequark b00e55a16a
Merge pull request #2522 from tomverbeure/simlib_typos2 
Fix some trivial typos.
 2021-01-04 14:04:17 +00:00
Xiangyu Xu c4e23aab55
Add boost-python3 
If enable python-api, do need boost-python3.
 2021-01-04 03:23:09 -06:00