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688 Commits

Author SHA1 Message Date
Henner Zeller 68b5d0c3b1 Convert more log_error() to log_file_error() where possible. 
Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
 2018-07-20 09:37:44 -07:00
Henner Zeller b5ea598ef6 Use log_file_warning(), log_file_error() functions. 
Wherever we can report a source-level location.
 2018-07-20 08:19:06 -07:00
Henner Zeller 1a60126a34 Provide source-location logging. 
o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
 2018-07-19 10:22:02 -07:00
Clifford Wolf 65234d4b24 Fix handling of eventually properties in verific importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-17 12:43:30 +02:00
Clifford Wolf 5041ed2f7d Fix verific -vlog-incdir and -vlog-libdir handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 18:47:42 +02:00
Clifford Wolf f897af626d Fix "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 16:48:09 +02:00
Clifford Wolf f39b897545 Add "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 15:32:26 +02:00
Clifford Wolf 8b92ddb9d2 Fix verific eventually handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 19:24:58 +02:00
Clifford Wolf 0404cf61d5 Add verific support for eventually properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 19:21:04 +02:00
Clifford Wolf ebf0f003d3 Add "verific -formal" and "read -formal" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 10:02:27 +02:00
Clifford Wolf afedb2d03e Add "read -sv -D" support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:58:15 +02:00
Clifford Wolf 07e616900c Add "read -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:43:38 +02:00
Clifford Wolf fe2ee833e1 Fix handling of signed memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 16:57:03 +02:00
Clifford Wolf 848c3c5c88 Add YOSYS_NOVERIFIC env variable for temporarily disabling verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-22 20:40:22 +02:00
Clifford Wolf d412b17259 Add simplified "read" command, enable extnets in implicit Verific import 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-21 16:56:55 +02:00
Clifford Wolf 5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf 0ff0ce4973 Bugfix in liberty parser (as suggested by aiju in #569) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-15 18:56:44 +02:00
Clifford Wolf 4372cf690d Add (* gclk *) attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 13:25:42 +02:00
Clifford Wolf 9a946c207f Add comment to VIPER #13453 work-around 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 13:36:35 +02:00
Clifford Wolf 001c9f1d45 Fix Verific handling of single-bit anyseq/anyconst wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 15:41:45 +02:00
Clifford Wolf 251562a491 Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 18:13:38 +02:00
Clifford Wolf 4d645f0fce Fix verific handling of anyconst/anyseq attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 17:07:06 +02:00
Jim Paris 4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
Jim Paris 872d8d49e9 Skip spaces around macro arguments 2018-05-17 00:06:49 -04:00
Clifford Wolf a7281930c5 Fix handling of anyconst/anyseq attrs in VHDL code via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 19:27:00 +02:00
Sergiusz Bazanski 7d076f071e Also interpret '&' in liberty functions 2018-05-12 20:55:31 +02:00
Clifford Wolf 24e6401617 Further improve handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 14:32:04 +02:00
Clifford Wolf 3e67497ec2 Fix handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 13:58:01 +02:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Dan Gisselquist e060375f23 Support more character literals 2018-05-03 12:35:01 +02:00
Clifford Wolf 2d7f3123f0 Add statement labels for immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-13 11:52:28 +02:00
Clifford Wolf 66ffc99695 Allow "property" in immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-12 14:28:28 +02:00
Clifford Wolf 617c60cea6 Add PRIM_HDL_ASSERTION support to Verific importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-07 18:38:42 +02:00
Clifford Wolf 0ac768f9df Fix handling of $global_clocking in Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 21:23:47 +02:00
Clifford Wolf 5ea2c53604 Add read_verilog anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:35:11 +02:00
Clifford Wolf 278685b084 Add Verific anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:19:55 +02:00
Clifford Wolf ab8db2c168 Add "verific -autocover" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:10:57 +02:00
makaimann 0c404b1f63 Set RAM runtime flags for Verific frontend 2018-04-05 17:38:08 -07:00
Clifford Wolf 93985d91b1 Remove left-over log_ping debug commands.. oops. 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-31 14:23:57 +02:00
Udi Finkelstein 6378e2cd46 First draft of Verilog parser support for specify blocks and parameters. 
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
 2018-03-27 14:34:00 +02:00
Clifford Wolf 315d5e32bf Fix handling of unclocked immediate assertions in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-26 13:04:10 +02:00
Clifford Wolf e7862d4f64 Update todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 15:48:48 +01:00
Clifford Wolf 38596ce68f Update todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 12:16:52 +01:00
Clifford Wolf 462e9f7bd4 Add todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 12:15:36 +01:00
Clifford Wolf 7cf9d88028 Improve import of memories via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-15 18:20:37 +01:00
Clifford Wolf bf402a806a Fix handling of SV compilation units in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-14 20:22:11 +01:00
Clifford Wolf 307c16a309 Fix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEAT 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 16:24:01 +01:00
Clifford Wolf ce37b6d730 Fix variable name typo in verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 14:33:42 +01:00
Clifford Wolf da216937b1 Add support for trivial SVA sequences and properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 14:32:01 +01:00
Clifford Wolf a15208f301 Use Verific hier_tree component for elaboration 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-08 13:26:33 +01:00