yosys

mirror of https://github.com/YosysHQ/yosys.git

Author	SHA1	Message	Date
Clifford Wolf	5e49ee5c2d	Fix tests/simple/specify.v Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-27 14:34:00 +02:00
Udi Finkelstein	6378e2cd46	First draft of Verilog parser support for specify blocks and parameters. The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST	2018-03-27 14:34:00 +02:00