riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
11,011 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Zachary Snow c18ddbcd82 verilog: impose limit on maximum expression width 
Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
 2021-03-04 15:20:52 -05:00