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657 Commits

Author SHA1 Message Date
github-actions[bot] bdf153d06c Bump version 2021-10-27 00:51:44 +00:00
github-actions[bot] ee230f2bb9 Bump version 2021-10-26 00:51:59 +00:00
Miodrag Milanovic b8624ad2ae Compile option for enabling async load verific support 2021-10-25 09:04:43 +02:00
github-actions[bot] 52ba31b1c0 Bump version 2021-10-22 01:00:39 +00:00
github-actions[bot] a0e9d9fef9 Bump version 2021-10-21 00:59:29 +00:00
Miodrag Milanovic bf79ff5927 If verific have vhdl lib it is required by other libs 2021-10-20 13:08:08 +02:00
Miodrag Milanovic 150ce305f9 Forgot to remove from main list 2021-10-20 12:37:22 +02:00
Miodrag Milanovic 17269ae59b Option to disable verific VHDL support 2021-10-20 10:02:58 +02:00
github-actions[bot] 69b2b13ddd Bump version 2021-10-20 00:56:49 +00:00
github-actions[bot] a15b01a777 Bump version 2021-10-18 00:56:23 +00:00
github-actions[bot] 0dd42d406d Bump version 2021-10-16 00:58:22 +00:00
github-actions[bot] a0f5ba8501 Bump version 2021-10-12 00:57:44 +00:00
github-actions[bot] d8f6d7b18d Bump version 2021-10-09 00:51:28 +00:00
github-actions[bot] 772b9a108a Bump version 2021-10-08 00:57:28 +00:00
Marcelina Kościelnicka 4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
github-actions[bot] 356ec7bb39 Bump version 2021-10-05 00:53:24 +00:00
github-actions[bot] f3ef579ac4 Bump version 2021-10-03 00:58:23 +00:00
github-actions[bot] 7a7df9a3b4 Bump version 2021-09-28 00:53:49 +00:00
Miodrag Milanovic 070cad5f4b Prepare for next release cycle 2021-09-27 16:24:43 +02:00
github-actions[bot] 1cac671c70 Bump version 2021-09-25 00:51:53 +00:00
github-actions[bot] 9432400ec8 Bump version 2021-09-22 00:54:54 +00:00
github-actions[bot] 3931b3a03f Bump version 2021-09-19 00:52:56 +00:00
github-actions[bot] c88eaea6e0 Bump version 2021-09-14 00:56:06 +00:00
github-actions[bot] f44110c625 Bump version 2021-09-11 00:50:11 +00:00
github-actions[bot] 1d61a911b7 Bump version 2021-09-10 00:55:14 +00:00
github-actions[bot] 50be8fd0c2 Bump version 2021-09-03 00:50:30 +00:00
github-actions[bot] fe9da25c40 Bump version 2021-09-01 00:55:51 +00:00
github-actions[bot] b20bb653ce Bump version 2021-08-31 00:51:55 +00:00
github-actions[bot] 1dbf91a8ef Bump version 2021-08-30 00:49:03 +00:00
github-actions[bot] 591fe72203 Bump version 2021-08-23 00:46:01 +00:00
github-actions[bot] 21e710eb55 Bump version 2021-08-21 00:48:23 +00:00
Miodrag Milanovic b59c427348 Make Verific extensions optional 2021-08-20 10:19:04 +02:00
github-actions[bot] 75a4cdfc8a Bump version 2021-08-18 00:51:20 +00:00
github-actions[bot] e6dd4db0af Bump version 2021-08-17 00:49:33 +00:00
github-actions[bot] 83c0f82dc8 Bump version 2021-08-15 00:50:04 +00:00
github-actions[bot] 539d4ee907 Bump version 2021-08-14 00:46:42 +00:00
Rupert Swarbrick ee2b5b7ed1 Generate an RTLIL representation of bind constructs 
This code now takes the AST nodes of type AST_BIND and generates a
representation in the RTLIL for them.

This is a little tricky, because a binding of the form:

    bind baz foo_t foo_i (.arg (1 + bar));

means "make an instance of foo_t called foo_i, instantiate it inside
baz and connect the port arg to the result of the expression 1+bar".
Of course, 1+bar needs a cell for the addition. Where should that cell
live?

With this patch, the Binding structure that represents the construct
is itself an AST::AstModule module. This lets us put the adder cell
inside it. We'll pull the contents out and plonk them into 'baz' when
we actually do the binding operation as part of the hierarchy pass.

Of course, we don't want RTLIL::Binding to contain an
AST::AstModule (since kernel code shouldn't depend on a frontend), so
we define RTLIL::Binding as an abstract base class and put the
AST-specific code into an AST::Binding subclass. This is analogous to
the AST::AstModule class.
 2021-08-13 17:11:35 -06:00
github-actions[bot] c8023e37d8 Bump version 2021-08-13 00:50:48 +00:00
github-actions[bot] bfcd08a323 Bump version 2021-08-12 00:49:51 +00:00
github-actions[bot] b96eb888cc Bump version 2021-08-11 00:52:20 +00:00
github-actions[bot] f368e2c7e6 Bump version 2021-08-10 00:52:49 +00:00
Marcelina Kościelnicka d25b9088c8 Refactor common parts of SAT-using optimizations into a helper. 
This also aligns the functionality:

- in all cases, the onehot attribute is used to create appropriate
  constraints (previously, opt_dff didn't do it at all, and share
  created one-hot constraints based on $pmux presence alone, which
  is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
  importing the SAT problem (previously only memory_share did this)
  — this avoids creating clauses for hard cells that are unlikely
  to help with proving the UNSATness needed for optimization
 2021-08-09 16:54:35 +02:00
github-actions[bot] d8fcf1ab25 Bump version 2021-08-08 00:50:48 +00:00
github-actions[bot] a24906a7d2 Bump version 2021-08-07 00:45:55 +00:00
github-actions[bot] 2e421feb0e Bump version 2021-08-05 00:51:08 +00:00
github-actions[bot] d8b0c3277f Bump version 2021-08-04 00:49:53 +00:00
github-actions[bot] ca8ad62696 Bump version 2021-08-03 00:55:22 +00:00
github-actions[bot] 10bcc4e192 Bump version 2021-08-02 00:50:24 +00:00
github-actions[bot] 12db9b4273 Bump version 2021-07-31 00:50:30 +00:00
github-actions[bot] 87ef1dd805 Bump version 2021-07-30 00:52:33 +00:00