yosys

Commit Graph

Author	SHA1	Message	Date
whitequark	3f4460a186	ice40: match memory inference attribute values case insensitive. LSE/Synplify use case insensitive matching.	2020-02-06 14:58:20 +00:00
whitequark	fc28bf55aa	ice40: add support for both 1364.1 and LSE RAM/ROM attributes. This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).	2020-02-06 14:58:20 +00:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	df0163cd2b	iCE40: set min bram efficiency to 2%	2015-06-20 09:31:19 +02:00
Clifford Wolf	752851954b	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
Clifford Wolf	b4d7a590e8	initialized iCE40 brams (mode 0)	2015-04-25 20:44:51 +02:00
Clifford Wolf	d6f7698f59	Added ice40 bram support	2015-04-24 00:06:50 +02:00

7 Commits