Eddie Hung
5fb27c071b
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
Eddie Hung
d032198fac
ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
2019-07-13 01:11:00 -07:00
Eddie Hung
7a912f22b2
Use Const::from_string() not its constructor...
2019-07-12 01:32:10 -07:00
Eddie Hung
28274dfb09
Off by one
2019-07-12 01:17:53 -07:00
Eddie Hung
e0e5d7d68e
Fix spacing
2019-07-12 01:15:22 -07:00
Eddie Hung
4de03bd5e6
Remove double push
2019-07-12 01:08:48 -07:00
Eddie Hung
62ac5ebd02
Map to and from this box if -abc9
2019-07-12 00:53:01 -07:00
Eddie Hung
0f5bddcd79
ice40_opt to handle this box and opt back to SB_LUT4
2019-07-12 00:52:31 -07:00
Eddie Hung
a79ff2501e
Add new box to cells_sim.v
2019-07-12 00:52:19 -07:00
Eddie Hung
c6e16e1334
_ABC macro will map and unmap to this new box
2019-07-12 00:51:37 -07:00
Eddie Hung
fc3d74616f
Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
2019-07-12 00:50:42 -07:00
whitequark
b700a4b1c5
synth_ice40: switch -relut to be always on.
2019-07-11 20:18:41 +00:00
whitequark
a8c5f7f41e
synth_ice40: fix help text typo. NFC.
2019-07-11 20:18:41 +00:00
Eddie Hung
6bbd286e03
Error out if -abc9 and -retime specified
2019-07-10 12:47:48 -07:00
Eddie Hung
03705f69f4
Update synth_ice40 -device doc to be relevant for -abc9 only
2019-06-28 09:49:01 -07:00
Eddie Hung
af8a5ae5fe
Extraneous newline
2019-06-27 16:12:20 -07:00
Eddie Hung
4daa746797
Remove noise from ice40/cells_sim.v
2019-06-27 16:11:39 -07:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
David Shah
0dd850e655
abc9: Add wire delays to synth_ice40
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-26 11:39:44 +01:00
Eddie Hung
63182ed57d
Fix and cleanup ice40 boxes for carry in/out
2019-06-22 14:27:41 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
acw1251
ce29ede801
Fixed small typo in ice40_unlut help summary
2019-06-19 16:39:46 -04:00
acw1251
0d888ee7ed
Fixed the help summary line for a few commands
2019-06-19 15:27:04 -04:00
Eddie Hung
97d2656375
Resolve comments from @daveshah1
2019-06-14 12:00:02 -07:00
Eddie Hung
ee428f73ab
Remove WIP ABC9 flop support
2019-06-14 10:37:52 -07:00
Eddie Hung
627a62a797
Make doc consistent
2019-06-14 10:32:46 -07:00
Eddie Hung
2052806d33
Fix LP SB_LUT4 timing
2019-06-13 08:24:33 -07:00
Eddie Hung
f9433cc34b
Remove abc_flop{,_d} attributes from ice40/cells_sim.v
2019-06-12 09:29:30 -07:00
Eddie Hung
352c532bb2
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-10 11:02:54 -07:00
Simon Schubert
abf90b0403
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
2019-06-10 11:49:08 +02:00
Eddie Hung
0092770317
Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)
2019-06-03 12:34:55 -07:00
Eddie Hung
4da25c76b3
Ooopsie
2019-06-03 09:33:42 -07:00
Eddie Hung
9f44a71715
Consistent with xilinx
2019-06-03 09:23:43 -07:00
Eddie Hung
eb08e71bd1
Merge branch 'xaig' into xc7mux
2019-05-31 13:03:03 -07:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Sylvain Munaut
4f9183d107
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-05-13 12:51:06 +02:00
Clifford Wolf
373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
...
Improve pmgen, Add "peepopt" pass with shift-mul pattern
2019-05-03 20:39:50 +02:00
Eddie Hung
8829cba901
Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
2019-05-02 11:25:34 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Clifford Wolf
d2d402e625
Run "peepopt" in generic "synth" pass and "synth_ice40"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:10:37 +02:00
Eddie Hung
1ea6d7920f
Cleanup ice40
2019-04-26 14:31:59 -07:00
Eddie Hung
91c3afcab7
Use nonblocking
2019-04-23 13:42:06 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Eddie Hung
d7f0700bae
Convert to use #945
2019-04-21 15:19:02 -07:00
Luke Wren
71da836300
ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments
2019-04-21 21:40:11 +01:00
Eddie Hung
af4652522f
ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set
2019-04-19 21:09:55 -07:00
Eddie Hung
2776925bcf
Make SB_DFF whitebox
2019-04-19 08:36:38 -07:00
Eddie Hung
19b660ff6e
Fix SB_DFF comb model
2019-04-18 23:07:16 -07:00
Eddie Hung
0919f36b88
Missing close bracket
2019-04-18 17:50:11 -07:00
Eddie Hung
cf66416110
Annotate SB_DFF* with abc_flop and abc_box_id
2019-04-18 17:46:53 -07:00
Eddie Hung
ca1eb98a97
Add SB_DFF* to boxes
2019-04-18 17:46:32 -07:00
Eddie Hung
4c327cf316
Use new -wb flag for ABC flow
2019-04-18 10:32:41 -07:00
Eddie Hung
9278192efe
Also update Makefile.inc
2019-04-18 09:58:34 -07:00
Eddie Hung
7b6ab937c1
Make SB_LUT4 a blackbox
2019-04-18 09:05:22 -07:00
Eddie Hung
8024f41897
Fix rename
2019-04-18 09:04:34 -07:00
Eddie Hung
ed5e75ed7d
Rename to abc_*.{box,lut}
2019-04-18 09:02:58 -07:00
Eddie Hung
8fd455c910
Update Makefile.inc too
2019-04-17 15:19:48 -07:00
Eddie Hung
c795e14d25
Reduce to three devices: hx, lp, u
2019-04-17 15:19:02 -07:00
Eddie Hung
5c0853fc51
Add up5k timings
2019-04-17 15:10:39 -07:00
Eddie Hung
3105a8a653
Update error message
2019-04-17 15:07:44 -07:00
Eddie Hung
6f3e5297db
Add "-device" argument to synth_ice40
2019-04-17 15:04:46 -07:00
Eddie Hung
671cca59a9
Missing abc_flop_q attribute on SPRAM
2019-04-17 14:44:08 -07:00
Eddie Hung
437fec0d88
Map to SB_LUT4 from fastest input first
2019-04-17 13:01:17 -07:00
Eddie Hung
58847df1b9
Mark seq output ports with "abc_flop_q" attr
2019-04-17 12:27:45 -07:00
Eddie Hung
1eade06671
Also update Makefile.inc
2019-04-17 12:27:02 -07:00
Eddie Hung
4fb9ccfcd8
synth_ice40 to use renamed files
2019-04-17 12:22:03 -07:00
Eddie Hung
42c33db22c
Rename to abc.*
2019-04-17 12:15:34 -07:00
Eddie Hung
c1ebe51a75
Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"
...
This reverts commit a7632ab332
.
2019-04-17 11:10:20 -07:00
Eddie Hung
a7632ab332
Try using an ICE40_CARRY_LUT primitive to avoid ABC issues
2019-04-17 11:10:04 -07:00
Eddie Hung
17fb6c3522
Fix spacing
2019-04-17 08:40:50 -07:00
Eddie Hung
743c164eee
Add SB_LUT4 to box library
2019-04-16 17:34:11 -07:00
Eddie Hung
7980118d74
Add ice40 box files
2019-04-16 16:39:30 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Clifford Wolf
9284cf92b8
Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:14:18 +01:00
Clifford Wolf
ff4c2a14ae
Fix typo in ice40_braminit help msg
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-09 13:24:55 -08:00
Clifford Wolf
2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit
...
iCE40 BRAM primitives init from file
2019-03-09 13:24:10 -08:00
Sylvain Munaut
5b6f591033
ice40: Run ice40_braminit pass by default
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
Sylvain Munaut
e71055cfe8
ice40: Add ice40_braminit pass to allow initialization of BRAM from file
...
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
Elms
cd2902ab1f
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
...
EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
2019-02-28 16:23:40 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
...
Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Clifford Wolf
2fe1c830eb
Bugfix in ice40_dsp
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Clifford Wolf
84999a7e68
Add ice40 test_dsp_map test case generator
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb
Add "synth_ice40 -dsp"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
7bf4e4a185
Improve iCE40 SB_MAC16 model
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 12:55:20 +01:00
Clifford Wolf
62493c91b2
Add first draft of functional SB_MAC16 model
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-19 14:47:27 +01:00
Eddie Hung
323dd0e608
synth_ice40 to have new -abc9 arg
2019-02-14 13:19:27 -08:00
David Shah
7ef2333497
ice40: Use abc -dress in synth_ice40
...
Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut
...
synth: add k-LUT mode
2019-01-02 15:44:57 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
17b2831356
synth_ice40: use 4-LUT coarse synthesis mode.
2019-01-02 08:25:55 +00:00
Clifford Wolf
5fa5dbbdda
Rename "fine:" label to "map:" in "synth_ice40"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 16:36:19 +01:00
Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt
...
equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf
ceffa66dbd
Merge pull request #730 from smunaut/ffssr_dont_touch
...
ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-16 15:50:42 +01:00
Clifford Wolf
0c69f1d777
Merge pull request #725 from olofk/ram4k-init
...
Only use non-blocking assignments of SB_RAM40_4K for yosys
2018-12-16 15:42:04 +01:00
Sylvain Munaut
add6ab9b2a
ice40: Honor the "dont_touch" attribute in FFSSR pass
...
This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-08 22:46:28 +01:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
...
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
Olof Kindgren
889297c62a
Only use non-blocking assignments of SB_RAM40_4K for yosys
...
In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.
Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.
This patch will change to use non-blocking assignments only for yosys
2018-12-06 21:45:59 +01:00
whitequark
6e559ee3c7
synth_ice40: split `map_gates` off `fine`.
2018-12-06 12:04:39 +00:00
whitequark
d9fa4387c9
synth_ice40: add -noabc option, to use built-in LUT techmapping.
...
This should be combined with -relut to get sensible results.
2018-12-05 17:13:46 +00:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
ea4870b126
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
2018-12-05 16:30:37 +00:00
whitequark
1719aa88ac
Extract ice40_unlut pass from ice40_opt.
...
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
2018-12-05 16:30:24 +00:00
Sylvain Munaut
3e5ab50a73
ice40: Add option to only use CE if it'd be use by more than X FFs
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
51f1bbeeb0
Add iCE40 SB_SPRAM256KA simulation model
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-10 11:57:24 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
David Shah
cd65eeb3b3
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:09:18 +02:00
Clifford Wolf
57fc8dd582
Add "synth_ice40 -json"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-13 13:35:10 +02:00
Clifford Wolf
83631555dd
Fix ice40_opt for cases where a port is connected to a signal with width != 1
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-11 18:12:42 +02:00
Olof Kindgren
faac2c5595
Avoid mixing module port declaration styles in ice40 cells_sim.v
...
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
2018-05-17 13:54:43 +02:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
...
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Tim 'mithro' Ansell
ca39e493ba
synth_ice40: Rework the vpr blif output slightly.
2018-04-18 16:55:08 -07:00
Clifford Wolf
81a457c4a6
Add "synth_ice40 -nodffe"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-16 20:44:26 +02:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
Graham Edgecombe
f93e6637aa
Fix port names in SB_IO_OD
2017-12-10 15:33:38 +00:00
Graham Edgecombe
52ace35a73
Remove trailing comma from SB_IO_OD port list
...
This isn't compatible with Icarus Verilog.
2017-12-10 15:33:38 +00:00
Tim Ansell
3cc31f197c
Fix spelling in -vpr help for synth_ice40
2017-12-08 18:44:45 -08:00
David Shah
5e8d1922a4
Add remaining UltraPlus cells to ice40 techlib
2017-11-28 11:07:49 +00:00
David Shah
0505f1043c
Remove unnecessary keep attributes
2017-11-18 17:53:21 +00:00
David Shah
8ae73e60e2
Merge branch 'master' into up5k
2017-11-17 15:15:39 +00:00
Clifford Wolf
234726c655
Add "synth_ice40 -vpr"
2017-11-16 21:37:02 +01:00
David Shah
f9f3ca5da0
Add some UltraPlus cells to ice40 techlib
2017-11-16 12:24:35 +00:00
Clifford Wolf
e64b9d5a4d
Fix synth_ice40 doc regarding -top default
2017-09-29 17:52:57 +02:00
Clifford Wolf
81bdf0ad0f
iCE40 flow is not experimental anymore
2016-11-01 11:32:02 +01:00
Clifford Wolf
21659847a7
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
2016-07-08 14:41:36 +02:00
Clifford Wolf
df5ebfa0a0
Improved ice40_ffinit error reporting
2016-06-30 09:58:13 +02:00
Clifford Wolf
ca91bccb6b
Added "deminout"
2016-06-19 13:08:16 +02:00
Clifford Wolf
6fe3d5a1cf
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Clifford Wolf
126da0ad3d
Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
2016-05-06 14:32:32 +02:00
Clifford Wolf
a24021ea20
Converted synth_greenpak4 to ScriptPass
2016-04-23 10:27:33 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
2553319081
Added ScriptPass helper class for script-like passes
2016-03-31 11:16:34 +02:00
Clifford Wolf
ec93680bd5
Renamed opt_share to opt_merge
2016-03-31 08:52:49 +02:00
Clifford Wolf
1d0f0d668a
Renamed opt_const to opt_expr
2016-03-31 08:46:56 +02:00
Clifford Wolf
0ccfb88728
Work around DDR dout sim glitches in ice40 SB_IO sim model
2016-02-07 11:19:48 +01:00
Clifford Wolf
d69395ca08
Added dffsr2dff
2016-02-02 17:19:01 +01:00
Clifford Wolf
2ee608246f
Re-run ice40_opt in "synth_ice40 -abc2"
2015-12-22 12:19:11 +01:00
Clifford Wolf
3102ffbb83
Improvements in ice40_opt
2015-12-22 12:18:38 +01:00
Clifford Wolf
8bf452c364
Bugfix in ice40_ffinit
2015-12-22 12:18:06 +01:00
Clifford Wolf
ec93d258a4
Improved ice40_ffinit
2015-12-22 11:15:25 +01:00
Clifford Wolf
494e5f24f9
Added "synth_ice40 -abc2"
2015-12-08 11:16:26 +01:00
Clifford Wolf
4d0a6dac7b
Merge pull request #108 from cseed/master
...
Added LO to ICESTORM_LC for LUT cascade route.
2015-12-07 03:32:20 +01:00
Cotton Seed
9f5b6e4cbc
Added LO to ICESTORM_LC for LUT cascade route.
2015-12-06 17:24:48 -05:00
Clifford Wolf
0793f1b196
Added ice40_ffinit pass
2015-11-26 18:11:06 +01:00
Clifford Wolf
8ff229a3ea
Fixed WE/RE usage in iCE40 BRAM mapping
2015-11-24 10:51:34 +01:00
Clifford Wolf
3ad742056b
Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling
2015-11-06 17:02:16 +01:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
99ccb3180d
Fixed ice40 handling of negclk RAM40
2015-09-10 17:35:19 +02:00
Clifford Wolf
c475deec6c
Switched to Python 3
2015-08-22 09:59:33 +02:00
Clifford Wolf
9596fe74de
Another bugfix for ice40 and xilinx brams_init make rules
2015-08-16 21:39:34 +02:00
Clifford Wolf
aedcfd6fd3
Fixed Makefile rules for generated share files
2015-08-16 21:15:07 +02:00
Clifford Wolf
9c33172ece
Added tribuf command
2015-08-16 12:55:25 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
c43f38c81b
Improved handling of "keep" attributes in hierarchical designs in opt_clean
2015-08-12 14:10:14 +02:00
Marcus Comstedt
c9e56bc428
Added iCE40 WARMBOOT cell
2015-08-06 22:58:17 +02:00
Clifford Wolf
516e8828f2
Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
2015-07-27 22:44:01 +02:00
Clifford Wolf
c6ca4780e2
iCE40 DFF sim models: init Q regs to 0
2015-07-20 13:05:18 +02:00
Clifford Wolf
54588a276a
Avoid tristate warning for blackbox ice40/cells_sim.v
2015-07-18 11:59:04 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
df0163cd2b
iCE40: set min bram efficiency to 2%
2015-06-20 09:31:19 +02:00
Clifford Wolf
9500b564ac
synth_ice40 now flattens by default
2015-06-09 20:28:17 +02:00
Clifford Wolf
09ef279b60
Added iCE40 PLL cells
2015-05-31 13:10:43 +02:00
Clifford Wolf
c329233f0d
Added output args to synth_ice40
2015-05-26 17:08:53 +02:00
Clifford Wolf
313f570fcc
improved ice40 SB_IO sim model
2015-05-23 10:17:03 +02:00
Clifford Wolf
264eb8eb6e
Added ice40 SB_IO sim model
2015-05-23 09:30:24 +02:00
Clifford Wolf
61512b6f41
Verific build fixes
2015-05-17 08:19:52 +02:00
Clifford Wolf
9d067fecea
ice40_opt bugfix
2015-04-27 11:36:13 +02:00
Clifford Wolf
310fde197e
iCE40: SB_CARRY const fold -> unmap SB_LUT
2015-04-27 10:27:50 +02:00
Clifford Wolf
8d4a675f91
Added iCE40 const folding support for SB_CARRY
2015-04-27 08:38:14 +02:00
Clifford Wolf
752851954b
Initialization support for all iCE40 bram modes
2015-04-26 08:39:31 +02:00
Clifford Wolf
b4d7a590e8
initialized iCE40 brams (mode 0)
2015-04-25 20:44:51 +02:00
Clifford Wolf
4cc4400514
improved iCE40 SB_RAM40_4K simulation model
2015-04-25 20:01:37 +02:00
Clifford Wolf
82a4722f46
More iCE40 bram improvements
2015-04-25 18:04:57 +02:00
Clifford Wolf
687f5a5b12
iCE40 bram progress
2015-04-24 15:38:11 +02:00
Clifford Wolf
308a59aa18
iCE40 bram tests and fixes
2015-04-24 08:32:07 +02:00
Clifford Wolf
d6f7698f59
Added ice40 bram support
2015-04-24 00:06:50 +02:00
Clifford Wolf
1277d1bcb8
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
2015-04-19 21:37:40 +02:00
Clifford Wolf
49ef830464
added sync reset to ice40 test_ffs.sh
2015-04-18 09:41:31 +02:00
Clifford Wolf
f564a65851
Added ice40 test_arith
2015-04-18 09:33:34 +02:00
Clifford Wolf
f78fa718be
Added ice40 SB_CARRY support
2015-04-18 09:33:08 +02:00
Clifford Wolf
661b647559
Added mapping of synchronous set/reset to iCE40 flow
2015-04-17 11:54:25 +02:00
Clifford Wolf
31755ed1cf
Changed ice40 ICESTORM_CARRYCONST port name
2015-04-16 12:09:14 +02:00
Clifford Wolf
dc30b034f7
Fixed "dff2dffe -direct-match"
2015-04-16 11:47:59 +02:00
Clifford Wolf
3e9e6e1c22
Added simple ice40 dff tests
2015-04-16 11:31:15 +02:00
Clifford Wolf
0d344a23d3
improved ice40 dff cell mapping
2015-04-16 11:30:56 +02:00
Clifford Wolf
4529c56cc6
use "hierarchy -auto-top" in synth_ice40
2015-04-14 13:45:15 +02:00
Clifford Wolf
06ce496f8d
more cells in ice40 cell library
2015-04-14 13:44:43 +02:00
Clifford Wolf
42d5d94a5d
Added very first version of "synth_ice40"
2015-03-05 20:37:55 +01:00