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2022-01-27 00:56:19 +00:00
Miodrag Milanovic
8a02616465
Add fstdata helper class
2022-01-26 10:23:38 +01:00
Miodrag Milanovic
9e9083bbe9
Add FST library
2022-01-25 09:53:41 +01:00
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Miodrag Milanovic
c428a894c0
Next dev cycle
2022-01-11 08:39:34 +01:00
Miodrag Milanovic
8b1eafc3ad
Release version 0.13
2022-01-11 08:35:50 +01:00
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Miodrag Milanovic
c23cd00f30
Next dev cycle
2021-12-03 12:51:34 +01:00
Miodrag Milanovic
2156e20db5
Release version 0.12
2021-12-03 12:48:49 +01:00
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2021-11-14 00:54:56 +00:00
Patrick Urban
0a72952d5f
synth_gatemate: Apply review remarks
...
* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
2021-11-13 21:53:25 +01:00
github-actions[bot]
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2021-11-13 00:52:01 +00:00
Miodrag Milanovic
48a628522b
update abc
2021-11-12 12:40:24 +01:00
Miodrag Milanovic
b4f68e3cca
Update abc
2021-11-12 09:00:32 +01:00
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2021-11-06 00:51:08 +00:00
Miodrag Milanovic
a28ee81be0
Next dev cycle
2021-11-05 12:52:24 +01:00
Miodrag Milanovic
360fed8e4d
Release version 0.11
2021-11-05 12:47:38 +01:00
Miodrag Milanović
5a5244a12e
Merge pull request #3067 from YosysHQ/aki/ci_update
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Update the Linux and macOS CI jobs
2021-11-05 09:58:35 +01:00
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2021-11-01 01:05:04 +00:00
Aki Van Ness
ad81cff823
Changed the Makefile to have an explicit `CXXSTD` parameter which allows for the setting of other C++ standards, the default is `c++11`
2021-10-31 20:07:30 -04:00
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Miodrag Milanovic
32673edfea
Revert "Compile option for enabling async load verific support"
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This reverts commit b8624ad2ae
.
2021-10-27 15:55:43 +02:00
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Miodrag Milanovic
b8624ad2ae
Compile option for enabling async load verific support
2021-10-25 09:04:43 +02:00
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2021-10-21 00:59:29 +00:00
Daniel Huisman
25c4ed3beb
Fix emcc warnings for WebAssembly build
2021-10-20 14:43:30 +02:00
Miodrag Milanovic
bf79ff5927
If verific have vhdl lib it is required by other libs
2021-10-20 13:08:08 +02:00
Miodrag Milanovic
150ce305f9
Forgot to remove from main list
2021-10-20 12:37:22 +02:00
Miodrag Milanovic
17269ae59b
Option to disable verific VHDL support
2021-10-20 10:02:58 +02:00
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2021-10-08 00:57:28 +00:00
Marcelina Kościelnicka
4e70c30775
FfData: some refactoring.
...
- FfData now keeps track of the module and underlying cell, if any (so
calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
compilation
- the "flip FF data sense by inserting inverters in front and after"
functionality that zinit uses is moved onto FfData class and beefed up
to have dffsr support, to support more use cases
2021-10-07 04:24:06 +02:00
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2021-09-28 00:53:49 +00:00
Miodrag Milanovic
070cad5f4b
Prepare for next release cycle
2021-09-27 16:24:43 +02:00
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2021-08-21 00:48:23 +00:00
Miodrag Milanovic
b59c427348
Make Verific extensions optional
2021-08-20 10:19:04 +02:00
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2021-08-14 00:46:42 +00:00
Rupert Swarbrick
ee2b5b7ed1
Generate an RTLIL representation of bind constructs
...
This code now takes the AST nodes of type AST_BIND and generates a
representation in the RTLIL for them.
This is a little tricky, because a binding of the form:
bind baz foo_t foo_i (.arg (1 + bar));
means "make an instance of foo_t called foo_i, instantiate it inside
baz and connect the port arg to the result of the expression 1+bar".
Of course, 1+bar needs a cell for the addition. Where should that cell
live?
With this patch, the Binding structure that represents the construct
is itself an AST::AstModule module. This lets us put the adder cell
inside it. We'll pull the contents out and plonk them into 'baz' when
we actually do the binding operation as part of the hierarchy pass.
Of course, we don't want RTLIL::Binding to contain an
AST::AstModule (since kernel code shouldn't depend on a frontend), so
we define RTLIL::Binding as an abstract base class and put the
AST-specific code into an AST::Binding subclass. This is analogous to
the AST::AstModule class.
2021-08-13 17:11:35 -06:00
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2021-08-10 00:52:49 +00:00
Marcelina Kościelnicka
d25b9088c8
Refactor common parts of SAT-using optimizations into a helper.
...
This also aligns the functionality:
- in all cases, the onehot attribute is used to create appropriate
constraints (previously, opt_dff didn't do it at all, and share
created one-hot constraints based on $pmux presence alone, which
is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
importing the SAT problem (previously only memory_share did this)
— this avoids creating clauses for hard cells that are unlikely
to help with proving the UNSATness needed for optimization
2021-08-09 16:54:35 +02:00
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2021-07-27 00:52:14 +00:00
Miodrag Milanovic
7a5ac90985
Update to latest Verific with extensions for initial assertions
2021-07-09 09:02:27 +02:00
Xiretza
75e5500d4d
Makefile: allow running multiple sanitizers at once
2021-07-05 16:42:10 +02:00
Xiretza
a189284a28
Makefile: use git/make -C instead of cd
2021-07-05 16:42:01 +02:00
Xiretza
ef68c2762c
Makefile: pass PRETTY=0 to ABC
2021-07-05 16:40:48 +02:00
Xiretza
9c31ecfab8
Makefile: don't bake DESTDIR into libyosys DT_SONAME
...
DESTDIR is only used as a temporary destination for installed files
before they are packaged into an archive; the "real" installed location
is determined by PREFIX/{BIN,LIB,DAT}DIR.
2021-07-05 16:39:16 +02:00
Xiretza
18f4ae482c
Makefile: clean up PYOSYS configuration
2021-07-05 16:38:58 +02:00
Ashton Snelgrove
092f0cb01e
Include blif reader header in public facing extension header files.
2021-06-16 22:29:34 +02:00
Claire Xenia Wolf
0ada13cbe2
Use HTTPS for website links, gatecat email
...
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
...
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
1eea06bcc0
Add new helper class for merging FFs into cells, use for memory_dff.
...
Fixes #1854 .
2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka
25de8faf10
Bump version
2021-05-20 12:50:32 +02:00
Marcelina Kościelnicka
32a0ce9d68
blif: Use library cells' start_offset and upto for wideports.
...
Fixes #2729 .
2021-05-08 15:50:03 +02:00
Marcelina Kościelnicka
687f381b69
Bump version
2021-03-30 02:30:17 +02:00
Lofty
f4298b057a
quicklogic: PolarPro 3 support
...
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
Marcelina Kościelnicka
0b0e219765
Bump version
2021-03-08 20:18:11 +01:00
Marcelina Kościelnicka
0e0f84299a
Bump version
2021-03-01 19:33:05 +01:00
Marcelina Kościelnicka
5d0cc54f5c
Bump version
2021-02-26 00:24:33 +01:00
William D. Jones
9cb0bae1b2
machxo2: Add test/arch/machxo2 directory (test does not pass).
2021-02-23 17:39:58 +01:00
Yosys Bot
127484e675
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2021-02-18 00:10:06 +00:00
Yosys Bot
78684596dc
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Yosys Bot
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Yosys Bot
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Yosys Bot
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Yosys Bot
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Yosys Bot
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2021-01-02 00:10:04 +00:00
umarcor
7f28afd3ac
makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX
2020-12-30 07:06:52 +01:00
Yosys Bot
48d0aeb094
Bump version
2020-12-30 00:10:06 +00:00
whitequark
e609bc4898
Merge pull request #2514 from umarcor/feat/ghdl
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makefile: add support for built-in ghdl-yosys-plugin
2020-12-29 02:58:41 +00:00
Yosys Bot
0347b441a1
Bump version
2020-12-29 00:10:04 +00:00
umarcor
a652430c71
makefile: add support for built-in ghdl-yosys-plugin
...
Co-authored-by: Tristan Gingold <tgingold@free.fr>
Co-authored-by: whitequark <whitequark@whitequark.org>
2020-12-28 22:45:00 +01:00
umarcor
0ebce301c1
makefile: rename msys2 to msys2-32, config PREFIX
2020-12-28 02:23:04 +01:00