Udi Finkelstein
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6378e2cd46
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First draft of Verilog parser support for specify blocks and parameters.
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
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2018-03-27 14:34:00 +02:00 |
Clifford Wolf
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dbfd8460a9
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Allow $size and $bits in verilog mode, actually check test case
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2017-09-29 11:56:43 +02:00 |
Udi Finkelstein
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e951ac0dfb
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$size() now works correctly for all cases!
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
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2017-09-26 20:34:24 +03:00 |
Udi Finkelstein
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6ddc6a7af4
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$size() seems to work now with or without the optional parameter.
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
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2017-09-26 19:18:25 +03:00 |
Udi Finkelstein
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2dea42e903
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Added $bits() for memories as well.
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2017-09-26 09:11:25 +03:00 |
Udi Finkelstein
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17f8b41605
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$size() now works with memories as well!
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2017-09-26 08:36:45 +03:00 |
Udi Finkelstein
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64eb8f29ad
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Add $size() function. At the moment it works only on expressions, not on memories.
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2017-09-26 06:25:42 +03:00 |
Larry Doolittle
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2021ddecb3
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Squelch trailing whitespace
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2017-04-12 15:11:09 +02:00 |
Clifford Wolf
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080004b19a
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Fixed typo in tests/simple/arraycells.v
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2017-01-04 12:39:01 +01:00 |
Clifford Wolf
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70d7a02cae
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Added support for hierarchical defparams
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2016-11-15 13:35:19 +01:00 |
Eric Smith
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f4240cc8a4
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
Clifford Wolf
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450f6f59b4
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Fixed bug with memories that do not have a down-to-zero data width
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2016-08-22 14:27:46 +02:00 |
Clifford Wolf
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cdd0b85e47
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Added another mem2reg test case
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2016-08-21 13:45:46 +02:00 |
Clifford Wolf
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82a4a0230f
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Another bugfix in mem2reg code
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2016-08-21 13:23:58 +02:00 |
Clifford Wolf
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9a101dc1f7
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Fixed mem assignment in left-hand-side concatenation
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2016-07-08 14:31:06 +02:00 |
Clifford Wolf
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7a4ee5da74
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Fixed init issue in mem2reg_test2 test case
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2016-06-17 20:15:11 +02:00 |
Clifford Wolf
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11f7b8a2a1
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Added opt_expr support for div/mod by power-of-two
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2016-05-29 12:17:36 +02:00 |
Clifford Wolf
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1761d08dd2
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Bugfix and improvements in memory_share
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2016-04-21 14:22:58 +02:00 |
Clifford Wolf
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0f94902125
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Added tests/simple/graphtest.v
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2015-11-30 11:41:12 +01:00 |
Clifford Wolf
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7ae3d1b5a9
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More bugfixes in handling of parameters in tasks and functions
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2015-11-12 13:02:36 +01:00 |
Clifford Wolf
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34f2b84fb6
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Fixed handling of parameters and localparams in functions
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2015-11-11 10:54:35 +01:00 |
Clifford Wolf
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ddf3e2dc65
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Bugfix in memory_dff
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2015-10-31 22:01:41 +01:00 |
Clifford Wolf
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ccdbf41be6
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Improvements in wreduce
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2015-10-31 13:39:30 +01:00 |
Larry Doolittle
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6c00704a5e
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Another block of spelling fixes
Smaller this time
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2015-08-14 23:27:05 +02:00 |
Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
Clifford Wolf
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e9368a1d7e
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Various fixes for memories with offsets
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2015-02-14 14:21:15 +01:00 |
Clifford Wolf
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dcf2e24240
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Added $meminit support to "memory" command
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2015-02-14 12:55:03 +01:00 |
Clifford Wolf
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913c304fe6
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Added $meminit test case
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2015-02-14 11:26:20 +01:00 |
Clifford Wolf
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694cc01f1d
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improvements in muxtree/select_leaves test
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2015-01-18 13:24:01 +01:00 |
Clifford Wolf
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f630868bc9
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Improvements in opt_muxtree
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2015-01-18 12:57:36 +01:00 |
Clifford Wolf
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f9c096eeda
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Added support for task and function args in parentheses
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2014-10-27 13:21:57 +01:00 |
Clifford Wolf
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cad98bcd89
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Added multi-dim memory test (requires iverilog git head)
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2014-08-12 10:37:47 +02:00 |
Clifford Wolf
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91dd87e60b
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Improved scope resolution of local regs in Verilog+AST frontend
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2014-08-05 12:15:53 +02:00 |
Clifford Wolf
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0129d41efa
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Fixed AST handling of variables declared inside a functions main block
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2014-08-05 08:35:51 +02:00 |
Clifford Wolf
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7d98645fe8
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Added "make -j{N}" support to "make test"
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2014-07-30 19:23:26 +02:00 |
Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
Clifford Wolf
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50f22ff30c
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
Clifford Wolf
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9b183539af
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Implemented dynamic bit-/part-select for memory writes
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2014-07-17 16:49:23 +02:00 |
Clifford Wolf
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5867f6bcdc
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Added support for bit/part select to mem2reg rewriter
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2014-07-17 13:49:32 +02:00 |
Clifford Wolf
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6d69d4aaa8
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Added support for constant bit- or part-select for memory writes
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2014-07-17 13:13:21 +02:00 |
Clifford Wolf
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964a67ac41
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Added note to "make test": use git checkout of iverilog
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2014-07-16 10:03:07 +02:00 |
Clifford Wolf
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ee8ad72fd9
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fixed parsing of constant with comment between size and value
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2014-07-02 06:27:04 +02:00 |
Clifford Wolf
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076182c34e
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Fixed handling of mixed real/int ternary expressions
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2014-06-25 10:05:36 +02:00 |
Clifford Wolf
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3345fa0bab
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Little steps in realmath test bench
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2014-06-21 21:43:04 +02:00 |
Clifford Wolf
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df76da8fd7
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Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:49:59 +02:00 |
Clifford Wolf
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398482eced
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Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)
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2014-06-15 09:39:22 +02:00 |
Clifford Wolf
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a4ec19c25c
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Added tests/realmath to "make test"
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2014-06-15 09:31:03 +02:00 |
Clifford Wolf
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f3b4a9dd24
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Added support for math functions
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2014-06-14 13:36:23 +02:00 |
Clifford Wolf
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406f86a91e
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Added realexpr.v test case
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2014-06-14 12:01:17 +02:00 |
Clifford Wolf
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3af7c69d1e
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added tests for new verilog features
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2014-06-07 12:26:11 +02:00 |
Clifford Wolf
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c82db39935
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Added tests/simple/repwhile.v
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2014-06-06 17:47:20 +02:00 |
Clifford Wolf
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a67cd2d4a2
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Progress in Verific bindings
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2014-03-17 01:56:00 +01:00 |
Clifford Wolf
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a6750b3753
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
Clifford Wolf
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4df7e03ec9
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Bugfix in name resolution with generate blocks
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2014-01-30 15:01:28 +01:00 |
Clifford Wolf
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fb2bf934dc
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Added correct handling of $memwr priority
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2014-01-03 00:22:17 +01:00 |
Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
Clifford Wolf
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994c83db01
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Added multiplier test case from eda playground
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2013-12-18 13:43:53 +01:00 |
Clifford Wolf
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fbd06a1afc
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Added elsif preproc support
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2013-12-18 13:41:36 +01:00 |
Clifford Wolf
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921064c200
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Added support for macro arguments
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2013-12-18 13:21:02 +01:00 |
Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
Clifford Wolf
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a2d053694b
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Fix in sincos testbench gen
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2013-12-04 09:24:52 +01:00 |
Clifford Wolf
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d1517b7982
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Added sincos test case
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2013-12-04 09:10:41 +01:00 |
Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
Clifford Wolf
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1e6836933d
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Added modelsim support to autotest
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2013-11-24 15:10:43 +01:00 |
Clifford Wolf
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65ad556f3d
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Another name resolution bugfix for generate blocks
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2013-11-20 13:57:40 +01:00 |
Clifford Wolf
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92035fb38e
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Implemented indexed part selects
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2013-11-20 13:05:27 +01:00 |
Clifford Wolf
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19dba2561e
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Implemented part/bit select on memory read
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2013-11-20 10:51:32 +01:00 |
Clifford Wolf
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c5e26f839c
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Added additional mem2reg testcase
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2013-11-18 19:55:39 +01:00 |
Clifford Wolf
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2a25e3bca3
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Fixed parsing of default cases when not last case
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2013-11-18 16:10:50 +01:00 |
Clifford Wolf
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fc6dc0d7b8
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
Clifford Wolf
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ada80545fa
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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
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2013-11-02 21:13:01 +01:00 |
Clifford Wolf
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943329c1dc
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Various ast changes for early expression width detection (prep for constfold fixes)
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2013-11-02 13:00:17 +01:00 |
Clifford Wolf
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628b994cf6
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Added support for complex set-reset flip-flops in proc_dff
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2013-10-24 16:54:05 +02:00 |
Clifford Wolf
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d61699843f
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Improved handling of dff with async resets
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2013-10-21 14:51:58 +02:00 |
Clifford Wolf
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759852914d
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Added support for "2**n" shifter encoding
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2013-08-12 14:47:50 +02:00 |
Clifford Wolf
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c8763301b4
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Added $div and $mod technology mapping
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2013-08-09 17:09:24 +02:00 |
Clifford Wolf
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3650fd7fbe
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More fixes in ternary op sign handling
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2013-07-12 13:13:04 +02:00 |
Clifford Wolf
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ded769c98c
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Fixed sign handling in ternary operator
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2013-07-12 01:15:37 +02:00 |
Clifford Wolf
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b380c8c790
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Another vloghammer related bugfix
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2013-07-11 19:24:59 +02:00 |
Clifford Wolf
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5dab327b30
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More fixes in ast expression sign/width handling
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2013-07-09 23:41:43 +02:00 |
Clifford Wolf
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618b2ac994
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-07-09 19:00:10 +02:00 |
Clifford Wolf
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7daeee340a
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Fixed shift ops with large right hand side
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2013-07-09 18:59:59 +02:00 |
Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
Clifford Wolf
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e8da3ea7b6
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Fixed another bug found using vloghammer
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2013-07-07 16:49:30 +02:00 |
Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
Clifford Wolf
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e0c408cb4a
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
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2013-04-13 21:19:10 +02:00 |
Clifford Wolf
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5640b7d607
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
Clifford Wolf
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d9bc024d29
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Renamed hansimem.v test case to mem_arst.v
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2013-03-24 15:25:08 +01:00 |
Clifford Wolf
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c3c9e5a02f
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Added hansimem testcase (memory with async reset)
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2013-03-24 10:40:40 +01:00 |
Johann Glaser
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3cfbc18601
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added ckeck for Icarus Verilog, otherwise the tests are silently stopped
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2013-03-17 09:05:15 +01:00 |
Clifford Wolf
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2d9cbd3b02
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added more .gitignore files (make test)
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2013-01-05 11:35:52 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |