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6650 Commits

Author SHA1 Message Date
Eddie Hung 08139aa53a xilinx_srl now copes with word-level flops $dff{,e} 2019-08-23 12:22:46 -07:00
Eddie Hung 18b64609c2 xilinx_srl to use 'slice' features of pmgen for word level 2019-08-23 12:22:06 -07:00
Eddie Hung f4fd41d5d2 Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl 2019-08-23 11:35:06 -07:00
Eddie Hung 78b7d8f531 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-23 11:32:44 -07:00
Eddie Hung 509c353fe9 Forgot one 2019-08-23 11:23:50 -07:00
Eddie Hung a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung bb2d5bc4f8
Merge pull request #1326 from mmicko/doc-update 
Make macOS dependency clear
 2019-08-23 09:12:58 -07:00
Clifford Wolf 55bf8f69e0 Fix port hanlding in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-23 16:26:54 +02:00
Clifford Wolf adb81ba386 Add pmgen slices and choices 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-23 16:15:50 +02:00
Miodrag Milanovic c618ae43b9 Make macOS depenency clear 2019-08-23 10:37:50 +02:00
Eddie Hung fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung 2b37a093e9 In sat: 'x' in init attr should not override constant 2019-08-22 16:42:19 -07:00
Eddie Hung 66607845ec Remove Xilinx test 2019-08-22 16:18:07 -07:00
Eddie Hung 53fed4f7e9 Actually, there might not be any harm in updating sigmap... 2019-08-22 16:16:56 -07:00
Eddie Hung cfafd360d5 Add comment as per @cliffordwolf 2019-08-22 16:16:56 -07:00
Eddie Hung e7a8cdbccf Add shregmap -tech xilinx test 2019-08-22 16:16:54 -07:00
Eddie Hung 8691596d19 Revert "Try way that doesn't involve creating a new wire" 
This reverts commit 2f427acc9e.
 2019-08-22 16:16:34 -07:00
Eddie Hung 5ff75b1cdc Try way that doesn't involve creating a new wire 2019-08-22 16:16:34 -07:00
Eddie Hung e1fff34dde If d_bit already in sigbit_chain_next, create extra wire 2019-08-22 16:16:34 -07:00
Eddie Hung c50d68653d Spelling 2019-08-22 16:06:36 -07:00
Eddie Hung 2fe35f902b
Merge pull request #1322 from mmicko/pyosys_osx 
do not require boost if pyosys is not used
 2019-08-22 11:53:27 -07:00
Eddie Hung 6e8fda8bf0 Add doc 2019-08-22 11:52:24 -07:00
Miodrag Milanovic e5dac8096d do not require boost if pyosys is not used 2019-08-22 20:43:52 +02:00
Eddie Hung 926cd10350
Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk 
require tcl-tk in Brewfile
 2019-08-22 11:32:44 -07:00
Eddie Hung cabadb85e2 Add copyright 2019-08-22 11:25:19 -07:00
Eddie Hung 7a9031c48e Add CHANGELOG entry 2019-08-22 11:22:53 -07:00
Eddie Hung 36d94caec1 Remove `shregmap -tech xilinx` additions 2019-08-22 11:22:09 -07:00
Eddie Hung 9f3ed1726e pmgen to also iterate over all module ports 2019-08-22 11:15:16 -07:00
Eddie Hung 74bd190d3b Remove output_bits 2019-08-22 11:14:59 -07:00
Eddie Hung 231ddbf95c Forgot to set ud_variable.minlen 2019-08-22 11:02:17 -07:00
Eddie Hung 61639d5387 Do not run xilinx_srl_pm in fixed loop 2019-08-22 10:51:04 -07:00
Eddie Hung 7188972645 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:54 -07:00
Eddie Hung d0b2973413 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:06 -07:00
Eddie Hung b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx 
opt_expr to trim A port of $shiftx/$shift
 2019-08-22 10:31:27 -07:00
Clifford Wolf e9f3eb9760 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:16 +02:00
Clifford Wolf 151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:09:37 +02:00
Clifford Wolf 2c8c8b3c74
Merge pull request #1289 from mmicko/anlogic_fixes 
Anlogic fixes and optimization
 2019-08-22 18:09:10 +02:00
Clifford Wolf 4c449caf9b Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:06:36 +02:00
Clifford Wolf 4d37710e82
Merge pull request #1281 from mmicko/efinix 
Initial support for Efinix Trion series FPGAs
 2019-08-22 18:06:02 +02:00
Eddie Hung 9245f0d3f5 Copy-paste typo 2019-08-22 08:43:44 -07:00
Chris Shucksmith d0322e9584 require tcl-tk in Brewfile 2019-08-22 16:37:40 +01:00
Eddie Hung 6f971470f8 Respect opt_expr -keepdc as per @cliffordwolf 2019-08-22 08:37:27 -07:00
Eddie Hung 379f33af54 Handle $shift and Y_WIDTH > 1 as per @cliffordwolf 2019-08-22 08:22:23 -07:00
Eddie Hung 9e31f01b34 Add cover() 2019-08-22 08:06:24 -07:00
Eddie Hung d0ffe7544c Canonical form 2019-08-22 08:05:01 -07:00
Clifford Wolf 34a7c0209d
Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg 
mem2reg to preserve user attributes and src
 2019-08-22 10:24:42 +02:00
Eddie Hung bb1a8a0190 Add test 2019-08-21 21:58:20 -07:00
Eddie Hung d3a212ff91 opt_expr to trim A port of $shiftx if Y_WIDTH == 1 2019-08-21 21:53:55 -07:00
Eddie Hung 7d02d17b16 Reuse var 2019-08-21 19:18:40 -07:00
Eddie Hung 5c8344363f Revert "Trim shiftx_width when upper bits are 1'bx" 
This reverts commit 7e7965ca7b.
 2019-08-21 19:18:27 -07:00