5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser
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Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 08:40:45 +00:00
8a84674a42
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 04:22:00 +00:00
7f1d83c5db
Add .gitignore to tests/select/
2020-04-12 22:45:45 +02:00
87555c44d5
Merge pull request #1907 from YosysHQ/dave/fix-1906
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verilog: Fix write to deleted object
2020-04-12 21:08:02 +01:00
0a178de1b3
verilog: Fix write to deleted object
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-12 18:49:09 +01:00
e300766fb3
Use `pool` instead of `std::set`.
2020-04-11 09:41:09 +00:00
73bd7fb01d
Use `dict` instead of `std::map`.
2020-04-11 06:53:59 +00:00
85672a6c1f
memory_bram: Fix ignorance of valid, matched rules
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-10 21:48:04 +01:00
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
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ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
93c6c67798
Merge pull request #1893 from mmicko/program_prefix
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Support custom PROGRAM_PREFIX
2020-04-10 16:33:01 +02:00
af7b7b6dc1
Keep libyosys name same as befire, but put it in directory
2020-04-10 15:02:48 +02:00
0d789c5a3b
Support custom PROGRAM_PREFIX
2020-04-10 10:38:40 +02:00
7c06cb6157
Merge pull request #1562 from whitequark/write_cxxrtl
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write_cxxrtl: new backend
2020-04-10 01:24:31 +00:00
371af7da38
Merge pull request #1858 from YosysHQ/eddie/fix1856
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kernel: include "kernel/constids.inc"
2020-04-09 14:23:47 -07:00
f11dd6e208
tests: add a quick plugin test
2020-04-09 09:45:20 -07:00
60ffc21e64
kernel: include "kernel/constids.inc" instead of "constids.inc"
2020-04-09 09:14:03 -07:00
516857f3ba
[NFCI] Deduplicate builtin FF cell types list
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A few passes included the same list of FF cell types. Make it a global
const instead.
The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
2020-04-09 18:05:06 +02:00
7f33d43e3b
Merge pull request #1890 from boqwxp/cleanup_memory_collect
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Clean up `passes/memory/memory_collect.cc`.
2020-04-09 14:01:29 +02:00
ed738b8ddb
Merge pull request #1889 from boqwxp/cleanup_memory_unpack
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Clean up `passes/memory/memory_unpack.cc`.
2020-04-09 14:00:44 +02:00
14d24bc589
Merge pull request #1887 from boqwxp/cleanup_hilomap
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Clean up `passes/techmap/hilomap.cc`.
2020-04-09 12:09:44 +02:00
de5e6fa56a
Clean up `passes/sat/qbfsat.cc`.
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Makes various cosmetic fixes, removes superfluous `hasPort()` check, and uses `emplace_back()` instead of `push_back()`.
2020-04-09 07:47:44 +00:00
652050b273
Clean up `passes/memory/memory_collect.cc`.
2020-04-09 05:43:05 +00:00
685dc37d27
Clean up `passes/memory/memory_unpack.cc`.
2020-04-09 05:38:36 +00:00
83222193af
Clean up `passes/techmap/hilomap.cc`.
2020-04-09 05:28:32 +00:00
4737f426ff
write_cxxrtl: add basic documentation.
2020-04-09 04:08:36 +00:00
753e34007d
write_cxxrtl: add support for $dlatch and $dlatchsr cells.
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Also, fix codegen for $dffe and $adff.
2020-04-09 04:08:36 +00:00
711df56ad0
write_cxxrtl: add support for $sr cell.
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Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
2020-04-09 04:08:36 +00:00
9534b51277
write_cxxrtl: add support for $slice and $concat cells.
2020-04-09 04:08:36 +00:00
01e6850bd3
write_cxxrtl: improve writable memory handling.
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This commit reduces space and time overhead for writable memories
to O(write port count) in both cases; implements handling for write
port priorities; and simplifies runtime representation of memories.
2020-04-09 04:08:36 +00:00
fb0270b752
write_cxxrtl: add support for hierarchical designs.
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Hierarchical design simulations are generally much slower, but this
comes with a major increase in flexibility:
1. Since the `flatten` pass currently does not support flattening
of designs with processes, this is the only way to simulate such
designs with cxxrtl.
2. Support for hierarchy paves way for simulation black boxes,
which are necessary for e.g. replacing PHYs with C++ code that
integrates with the host system.
2020-04-09 04:08:36 +00:00
3376dcf37c
write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.
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After this commit, if NDEBUG is not defined, out-of-bounds accesses
cause assertion failures for reads and writes. If NDEBUG is defined,
out-of-bounds reads return zeroes, and out-of-bounds writes are
ignored.
This commit also adds support for memories that start with a non-zero
index (`Memory::start_offset` in RTLIL).
2020-04-09 04:08:36 +00:00
5157691f0e
write_cxxrtl: statically schedule comb logic and localize wires.
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This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.
2020-04-09 04:08:36 +00:00
d6d7273421
write_cxxrtl: elide wires for results of comb cells used once.
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This results in massive gains in performance, equally massive
reduction in compile time, and improved readability.
2020-04-09 04:08:36 +00:00
d20e971725
write_cxxrtl: new backend.
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This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
2020-04-09 04:08:36 +00:00
42e7e44207
Merge pull request #1857 from whitequark/splitnets-skip-processes
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splitnets: skip modules with processes
2020-04-09 04:03:30 +00:00
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow
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Improve handling of integer literals in RTLIL frontend
2020-04-09 04:02:57 +00:00
570f43ec91
Merge pull request #1886 from boqwxp/cleanup_connect
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Clean up `passes/cmds/connect.cc`.
2020-04-09 03:58:07 +00:00
64a5936bd7
Clean up `passes/cmds/connect.cc`.
2020-04-08 22:11:06 +00:00
5f649fc19d
Add constids.inc to final install
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If this is not present in the install, #include-ing most yosys
headers will fail in rtlil.h:380.
2020-04-08 21:36:33 +02:00
5d18fdadfe
Merge pull request #1881 from hzeller/only-define-stdc-format-macros-if-not-already
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aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 13:56:40 -07:00
c15040c218
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
40223eaee1
Merge pull request #1814 from YosysHQ/mmicko/pyosys_makefile
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Enable ENABLE_LIBYOSYS when ENABLE_PYOSYS is set (closes #1813 )
2020-04-07 17:06:47 +02:00
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
194354e128
Remove `$anyconst` cells before specialization to eliminate warnings and the need to run `opt_clean`.
2020-04-07 03:29:54 +00:00
b350398c04
Merge pull request #1874 from boqwxp/cleanup_show
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Clean up `passes/cmds/show.cc`.
2020-04-06 18:32:20 +00:00
8ca12e0c42
Merge pull request #1861 from boqwxp/cleanup_hierarchy_submod
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Clean up `passes/hierarchy/submod.cc`.
2020-04-06 18:32:10 +00:00
b494d4c656
read_ilang: improve style. NFC.
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Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-06 18:31:15 +00:00
f4346a0400
Use more descriptive variable name.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-06 14:48:27 +00:00
d6de14a0d6
Use more descriptive variable name.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-06 14:37:07 +00:00
whitequark
Alberto Gonzalez
Xiretza
David Shah
Miodrag Milanović
Eddie Hung
Marcelina Kościelnicka
N. Engelhardt
Henner Zeller
Claire Wolf
Jeff Wang