Eddie Hung
db6a0b72b2
Reduce number of decomposed muxes during techmap
2019-06-24 14:28:56 -07:00
Eddie Hung
2e7992efff
Revert "Fix techmapping muxes some more"
...
This reverts commit 0aae3b4f43
.
2019-06-24 14:15:31 -07:00
Eddie Hung
7fbfcf20d1
Move comment
2019-06-24 14:15:00 -07:00
Eddie Hung
0aae3b4f43
Fix techmapping muxes some more
2019-06-24 12:50:48 -07:00
Eddie Hung
2b4501503d
Fix mux techmapping
2019-06-24 12:18:17 -07:00
Eddie Hung
aa1eeda567
Modify costs for muxcover
2019-06-24 11:51:55 -07:00
Eddie Hung
36e6da5396
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
Eddie Hung
d54dceb547
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-22 19:44:17 -07:00
Eddie Hung
792d0670c3
Add comment to xc7 box
2019-06-22 14:28:24 -07:00
Eddie Hung
7903ebe3e0
Carry in/out box ordering now move to end, not swap with end
2019-06-22 14:18:42 -07:00
Eddie Hung
65c022c257
Remove DFF and RAMD box info for now
2019-06-21 20:41:14 -07:00
Eddie Hung
bbf3ad90f5
Remove $_MUX4_ techmap rule
2019-06-21 18:12:33 -07:00
Eddie Hung
39e0e006d5
Fix wreduce call (!!!), tweak muxcover costs
2019-06-21 18:12:07 -07:00
Eddie Hung
faa2d6fc1c
Constrain wreduce only if wide mux
2019-06-21 17:12:34 -07:00
Eddie Hung
aeee9dcad7
Simplify and comment out mux_map.v
2019-06-21 17:06:30 -07:00
Eddie Hung
ed00823b41
synth_xilinx to now wreduce except $mux, remove extra peepopt
2019-06-21 16:56:56 -07:00
Eddie Hung
29aee0989f
mux_map to no longer copy last value into 1'bx
2019-06-21 16:55:59 -07:00
Eddie Hung
8bce3fb329
Fix spacing
2019-06-21 16:55:34 -07:00
Eddie Hung
694d40719f
Fix spacing again, A_forward -> A_backward
2019-06-21 16:47:07 -07:00
Eddie Hung
11886c874c
Restore wreduce to synth_xilinx, after muxcover
2019-06-21 16:18:29 -07:00
Eddie Hung
44fc616fc7
Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
2019-06-21 16:18:14 -07:00
Eddie Hung
4d6fac019a
Fix spacing
2019-06-21 16:06:13 -07:00
Eddie Hung
aa0b107afb
synth_xilinx to use _ABC macro, and perform muxpack again
2019-06-21 15:48:20 -07:00
Eddie Hung
9abde12110
Add $__XILINX_MUXF78 to preserve entire box
2019-06-21 15:47:42 -07:00
Eddie Hung
7acbea6b28
Fix alignment
2019-06-21 14:38:30 -07:00
Eddie Hung
f433a52374
Add FIXME about need for -mux4
2019-06-21 11:15:23 -07:00
Eddie Hung
c6b4653ebe
Since muxcover uses MUX4s, blast them back to gates here
2019-06-21 11:13:01 -07:00
Eddie Hung
dd22edcd28
Expand synth -coarse without wreduce, move muxcover
2019-06-21 11:12:32 -07:00
Eddie Hung
f11c9a419b
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
2019-06-20 17:38:16 -07:00
Eddie Hung
d1dadfcec8
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
2019-06-20 16:45:09 -07:00
Eddie Hung
9faab38e8d
mux_map to drop sign bit, and eliminate 'bx-es
2019-06-20 16:45:04 -07:00
Eddie Hung
4ca847a217
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-18 11:49:54 -07:00
Eddie Hung
8e0a47fb92
Really permute Xilinx LUT mappings as default LUT6.I5:A6
2019-06-18 11:48:48 -07:00
Eddie Hung
8f5e6d73ff
Revert "Fix (do not) permute LUT inputs, but permute mux selects"
...
This reverts commit da3d2eedd2
.
2019-06-18 11:35:21 -07:00
Eddie Hung
3d283e69f8
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-18 09:51:28 -07:00
Eddie Hung
da3d2eedd2
Fix (do not) permute LUT inputs, but permute mux selects
2019-06-18 09:49:57 -07:00
Eddie Hung
2b0e28b261
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 22:29:34 -07:00
Eddie Hung
608a95eb01
Fix copy-pasta issue
2019-06-17 22:29:22 -07:00
Eddie Hung
59b4e69d16
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 22:25:14 -07:00
Eddie Hung
2a35c4ef94
Permute INIT for +/xilinx/lut_map.v
2019-06-17 22:24:35 -07:00
Eddie Hung
75f8b4cf10
Simplify comment
2019-06-17 19:14:41 -07:00
Eddie Hung
75d92fb590
Merge branch 'xaig' into xaig_dff
2019-06-17 19:11:07 -07:00
Eddie Hung
9d56c0d525
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 18:25:35 -07:00
Eddie Hung
840562943f
Update LUT7/8 delays to take account for [ABC]OUTMUX delay
2019-06-17 17:06:01 -07:00
Eddie Hung
8a86f9bb62
Add box delays for FD*
2019-06-17 15:13:05 -07:00
Eddie Hung
5ce672d1c5
Merge remote-tracking branch 'origin/xaig' into xaig_dff
2019-06-17 12:14:55 -07:00
Eddie Hung
c15ee827f4
Try -W 300
2019-06-17 10:29:06 -07:00
Eddie Hung
1ec450d6bf
Try -W 300
2019-06-16 12:08:03 -07:00
Eddie Hung
0c59bc0b75
Cleanup
2019-06-16 10:42:00 -07:00
Eddie Hung
d969a9060e
Add +/xilinx/abc_ff
2019-06-15 22:41:29 -07:00
Eddie Hung
9ec57b46c2
Fix spacing
2019-06-15 19:36:37 -07:00
Eddie Hung
c2f3f116d0
Use $__ABC_FF_ instead of $_FF_
2019-06-15 18:16:14 -07:00
Eddie Hung
65c7bafc64
Re-order alphabetically
2019-06-15 10:19:05 -07:00
Eddie Hung
a76c8a7ffd
Fix initialisation of flops
2019-06-15 09:46:35 -07:00
Eddie Hung
ac18a76beb
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
2019-06-15 09:34:48 -07:00
Eddie Hung
295bb23ae0
Wrap FDRE with $__ABC_FDRE containing comb
2019-06-15 09:08:56 -07:00
Eddie Hung
842c110357
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-15 05:48:47 -07:00
Eddie Hung
bf312043d4
Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
2019-06-15 05:45:16 -07:00
Eddie Hung
b63b2a0bd4
Revert "Remove wide mux inference"
...
This reverts commit 738fdfe8f5
.
2019-06-14 12:50:24 -07:00
Eddie Hung
8fa74287a7
As per @daveshah1 remove async DFF timing from xilinx
2019-06-14 12:43:20 -07:00
Eddie Hung
2e34859a6b
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
2019-06-14 11:38:22 -07:00
Eddie Hung
ba4b4a0088
Update delays based on SymbiFlow/prjxray-db
2019-06-14 11:33:10 -07:00
Eddie Hung
d47ff7ba87
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
2019-06-14 10:51:11 -07:00
Eddie Hung
ee428f73ab
Remove WIP ABC9 flop support
2019-06-14 10:37:52 -07:00
Eddie Hung
627a62a797
Make doc consistent
2019-06-14 10:32:46 -07:00
Eddie Hung
75d89e56cf
Fix name clash
2019-06-13 14:27:07 -07:00
Eddie Hung
009255d11d
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-06-12 16:07:24 -07:00
Eddie Hung
c7f5091c2f
Reduce diff with master
2019-06-12 09:34:41 -07:00
Eddie Hung
99267f660f
Fix spacing
2019-06-12 09:21:52 -07:00
Eddie Hung
738fdfe8f5
Remove wide mux inference
2019-06-12 09:20:46 -07:00
Eddie Hung
1e838a8913
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
2019-06-12 08:49:15 -07:00
Eddie Hung
4c9fde87d1
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
...
This reverts commit 2dffa4685b
.
2019-06-12 08:48:45 -07:00
Eddie Hung
2dffa4685b
Add "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-11 17:10:47 -07:00
Eddie Hung
54379f9872
Disable dist RAM boxes due to comb loop
2019-06-11 12:02:51 -07:00
Eddie Hung
8a708d1fdb
Remove #ifndef ABC
2019-06-11 12:02:31 -07:00
Eddie Hung
b77c5da769
Revert "Revert "Move ff_map back after ABC for shregmap""
...
This reverts commit e473e74565
.
2019-06-10 14:37:09 -07:00
Eddie Hung
a1d4ae78a0
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
...
This reverts commit 94a5f4e609
.
2019-06-10 14:34:43 -07:00
Eddie Hung
816b5f5891
Comment out muxpack (currently broken)
2019-06-07 16:58:57 -07:00
Eddie Hung
88ae13e6a5
$__XILINX_MUX_ -> $__XILINX_SHIFTX
2019-06-06 15:32:36 -07:00
Eddie Hung
d3b7ae218b
Fix muxcover and its techmapping
2019-06-06 15:31:18 -07:00
Eddie Hung
a8c49168fb
Run muxpack and muxcover in synth_xilinx
2019-06-06 14:43:08 -07:00
Eddie Hung
7166dbe418
Remove abc_flop attributes for now
2019-06-06 14:35:38 -07:00
Eddie Hung
6ed15b7890
Update abc attributes on FD*E_1
2019-06-05 12:33:40 -07:00
Eddie Hung
67f744d428
Cleanup
2019-06-05 12:28:46 -07:00
Eddie Hung
2c18d530ea
Call shregmap -tech xilinx_static
2019-06-05 12:28:26 -07:00
Eddie Hung
e473e74565
Revert "Move ff_map back after ABC for shregmap"
...
This reverts commit 9b9bd4e19f
.
2019-06-05 11:53:06 -07:00
Eddie Hung
94a5f4e609
Rename shregmap -tech xilinx -> xilinx_dynamic
2019-06-04 14:34:36 -07:00
Eddie Hung
82d41bc2f2
Add space between -D and _ABC
2019-06-04 11:54:08 -07:00
Eddie Hung
f0e93f33cf
Add (* abc_flop_q *) to brams_bb.v
2019-06-04 11:53:51 -07:00
Eddie Hung
6cf092641f
Fix name clash
2019-06-04 09:56:36 -07:00
Eddie Hung
e260150321
Add mux_map.v for wide mux
2019-06-04 09:51:47 -07:00
Eddie Hung
9b9bd4e19f
Move ff_map back after ABC for shregmap
2019-06-03 23:43:23 -07:00
Eddie Hung
09b778744d
Respect -nocarry
2019-06-03 23:42:30 -07:00
Eddie Hung
5afa42432f
Fix pmux2shiftx logic
2019-06-03 23:29:45 -07:00
Eddie Hung
23a73ca624
Merge mistake
2019-06-03 23:19:22 -07:00
Eddie Hung
f81a0ed92e
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-03 23:07:08 -07:00
Eddie Hung
b6e59741ae
Typo
2019-06-03 20:21:41 -07:00
Eddie Hung
02973474df
Remove extra newline
2019-06-03 20:04:47 -07:00
Eddie Hung
c9a0bac541
IS_C_INVERTED
2019-06-03 19:45:56 -07:00
Eddie Hung
0ad50332d9
Execute techmap and arith_map simultaneously
2019-06-03 19:36:09 -07:00
Eddie Hung
ebcc85b9b8
Fix `ifndef
2019-06-03 12:37:02 -07:00
Eddie Hung
2228cef62f
Add flops as blackboxes
2019-05-31 18:11:46 -07:00
Eddie Hung
01f71085f2
Add FD*E_1 -> FD*E techmap rules
2019-05-31 18:11:24 -07:00
Eddie Hung
dea36d4366
Techmap flops before ABC again
2019-05-31 18:10:25 -07:00
Eddie Hung
eb08e71bd1
Merge branch 'xaig' into xc7mux
2019-05-31 13:03:03 -07:00
Eddie Hung
1ad33c3b5a
Remove whitebox attribute from DRAMs for now
2019-05-30 13:07:29 -07:00
Eddie Hung
fdfc18be91
Carry in/out to be the last input/output for chains to be preserved
2019-05-30 01:23:36 -07:00
Eddie Hung
276f5f8b81
Some more realistic delays...
2019-05-29 22:55:34 -07:00
Eddie Hung
f228621b80
Typo
2019-05-28 09:36:01 -07:00
Eddie Hung
e032e5bcde
Make MUXF{7,8} and CARRY4 whitebox
2019-05-27 23:09:06 -07:00
Eddie Hung
54e28eb3ea
Re-enable lib_whitebox
2019-05-27 23:08:55 -07:00
Eddie Hung
4311b9b583
Blackboxes
2019-05-26 11:32:02 -07:00
Eddie Hung
66701c5fcc
Muck about with LUT delays some more
2019-05-26 02:52:48 -07:00
Eddie Hung
ca5774ed40
Try new LUT delays
2019-05-24 20:39:55 -07:00
Eddie Hung
60af2ca94d
Transpose CARRY4 delays
2019-05-24 14:09:15 -07:00
Eddie Hung
52e9036d39
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-23 13:38:04 -07:00
Eddie Hung
99a3fee8f4
Add "min bits" and "min wports" to xilinx dram rules
2019-05-23 11:32:28 -07:00
Eddie Hung
ae89e6ab26
Add whitebox support to DRAM
2019-05-23 08:58:57 -07:00
Eddie Hung
4f44e3399b
shift register inference before mux
2019-05-22 02:36:28 -07:00
Eddie Hung
9b1078b9bd
Fix/workaround symptom unveiled by #1023
2019-05-21 18:50:02 -07:00
Eddie Hung
ee8435b820
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
Eddie Hung
36a219063a
Modify LUT area cost to be same as old abc
2019-05-21 14:31:19 -07:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Clifford Wolf
04ef222cfb
Add "stat -tech xilinx"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:24:52 +02:00
Clifford Wolf
09467bb9a3
Add "synth_xilinx -arch"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 15:04:36 +02:00
Eddie Hung
c2e29ab809
Rename cells_map.v to prevent clash with ff_map.v
2019-05-03 14:40:32 -07:00
Eddie Hung
283e33ba5a
Trim off leading 1'bx in A
2019-05-02 16:02:37 -07:00
Eddie Hung
fc72f07efd
Add don't care optimisation
2019-05-02 15:01:37 -07:00
Eddie Hung
d80445e049
Use new peepopt from #969
2019-05-02 11:35:57 -07:00
Eddie Hung
95867109ea
Revert to pre-muxcover approach
2019-05-02 11:25:10 -07:00
Eddie Hung
d05ac7257e
Missing help_mode
2019-05-02 11:14:28 -07:00
Eddie Hung
3b5e8c86a4
Fix -nocarry
2019-05-02 11:00:49 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Eddie Hung
d394b9301b
Back to passing all xc7srl tests!
2019-05-01 18:23:21 -07:00
Eddie Hung
31ff0d8ef5
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
2019-05-01 18:09:38 -07:00
Marcin Kościelnicki
98e5a625c4
synth_xilinx: Add -nocarry and -nomux options.
2019-04-30 12:54:21 +02:00
Eddie Hung
e97178a888
WIP
2019-04-28 12:51:00 -07:00
Eddie Hung
af840bbc63
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-28 12:36:04 -07:00
Eddie Hung
4aca928033
Fix spacing
2019-04-26 19:46:34 -07:00
Eddie Hung
d855683917
Revert synth_xilinx 'fine' label more to how it used to be...
2019-04-26 16:53:16 -07:00
Eddie Hung
ccc283737d
Apparently, this reduces number of MUXCY/XORCY
2019-04-26 16:28:48 -07:00
Eddie Hung
e31e21766d
Try a different approach with 'muxcover'
2019-04-26 16:09:54 -07:00
Eddie Hung
76b7c5d4cc
Merge remote-tracking branch 'origin/master' into xc7mux
2019-04-26 15:35:55 -07:00
Eddie Hung
ea0e0722bb
Where did this check come from!?!
2019-04-26 15:35:34 -07:00
Eddie Hung
6b9ca7cd6d
Remove split_shiftx call
2019-04-26 15:32:58 -07:00
Eddie Hung
8469d9fe9f
Missing newline
2019-04-26 14:51:37 -07:00
Eddie Hung
727eec04c5
Refactor synth_xilinx to auto-generate doc
2019-04-26 14:32:18 -07:00
Eddie Hung
f14d7f0df6
Cleanup superseded
2019-04-25 19:43:41 -07:00
Eddie Hung
019c48b508
bitblast_shiftx -> split_shiftx
2019-04-25 19:38:35 -07:00
Eddie Hung
feff976454
synth_xilinx to call bitblast_shiftx
2019-04-25 17:11:18 -07:00
Eddie Hung
f96d82a5f1
Add -nocarry option to synth_xilinx
2019-04-24 16:46:41 -07:00
Eddie Hung
0bd2bfa737
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 18:15:28 -07:00
Eddie Hung
60026842b2
Tweak
2019-04-22 17:59:56 -07:00
Eddie Hung
26e461f47d
Fix for A_WIDTH == 2 but B_WIDTH==3
2019-04-22 17:58:28 -07:00
Eddie Hung
1fa2c36fbd
Trim A_WIDTH by Y_WIDTH-1
2019-04-22 17:14:11 -07:00
Eddie Hung
69863f7698
Add comment
2019-04-22 16:58:44 -07:00
Eddie Hung
61161faefc
Fix for mux_case_* mappings
2019-04-22 16:56:18 -07:00
Eddie Hung
ac1e13819e
Fix for non-pow2 width muxes
2019-04-22 14:26:13 -07:00
Eddie Hung
75b96b1aff
Add synth_xilinx -nomux option
2019-04-22 12:36:15 -07:00
Eddie Hung
79fb291dbe
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 12:14:37 -07:00
Eddie Hung
4486a98fd5
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 11:45:49 -07:00
Eddie Hung
ec88129a5c
Update help message
2019-04-22 11:38:23 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Eddie Hung
0e76718720
Move 'shregmap -tech xilinx' into map_cells
2019-04-22 10:45:39 -07:00
Eddie Hung
e300b1922c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 10:36:27 -07:00
Clifford Wolf
cf1ba46fa0
Re-added clean after techmap in synth_xilinx
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 09:03:11 +02:00
Eddie Hung
d342b5b135
Tidy up, fix for -nosrl
2019-04-21 15:33:03 -07:00
Eddie Hung
726e2da8f2
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-21 14:28:55 -07:00
Eddie Hung
a3371e118b
Merge branch 'master' into map_cells_before_map_luts
2019-04-21 14:24:50 -07:00
Eddie Hung
ae95aba60a
Add comments
2019-04-21 14:16:59 -07:00
Eddie Hung
d99422411f
Use new pmux2shiftx from #944 , remove my old attempt
2019-04-21 14:16:34 -07:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Eddie Hung
13ad19482f
Merge remote-tracking branch 'origin' into xc7srl
2019-04-20 10:41:43 -07:00
Eddie Hung
6008bb7002
Revert "synth_* with -retime option now calls abc with -D 1 as well"
...
This reverts commit 9a6da9a79a
.
2019-04-18 07:59:16 -07:00
Eddie Hung
0642baabbc
Merge branch 'master' into eddie/fix_retime
2019-04-18 07:57:17 -07:00
Eddie Hung
cbb85e40e8
Add MUXCY and XORCY to cells_box.v
2019-04-16 14:53:28 -07:00
Eddie Hung
aece97024d
Fix spacing
2019-04-16 13:16:20 -07:00
Eddie Hung
53b19ab1f5
Make cells.box whiteboxes not blackboxes
2019-04-16 12:43:14 -07:00
Eddie Hung
5189695362
read_verilog cells_box.v before techmap
2019-04-16 12:41:56 -07:00
Eddie Hung
d259e6dc14
synth_xilinx: before abc read +/xilinx/cells_box.v
2019-04-16 11:21:46 -07:00
Eddie Hung
3ac4977b70
Add +/xilinx/cells_box.v containing models for ABC boxes
2019-04-16 11:21:03 -07:00
Eddie Hung
8c6cf07acf
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
...
This reverts commit 8fbbd9b129
.
2019-04-16 11:14:59 -07:00
Eddie Hung
8fbbd9b129
Add abc_box_id attribute to MUXF7/F8 cells
2019-04-15 22:25:09 -07:00
Eddie Hung
538592067e
Merge branch 'xaig' into xc7mux
2019-04-15 22:04:20 -07:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Keith Rothman
1f9235ede5
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-12 09:35:15 -07:00
Eddie Hung
233edf00fe
Fix cells_map.v some more
2019-04-11 10:48:14 -07:00
Eddie Hung
8658b56a08
More fine tuning
2019-04-11 10:08:05 -07:00
Eddie Hung
0ec8564099
Fix cells_map.v
2019-04-11 10:04:58 -07:00
Eddie Hung
bca3779657
Fix typo
2019-04-11 09:25:19 -07:00
Eddie Hung
87b8d29a90
Juggle opt calls in synth_xilinx
2019-04-11 09:13:39 -07:00
Eddie Hung
cd7b2de27f
WIP for cells_map.v -- maybe working?
2019-04-10 18:05:09 -07:00
Eddie Hung
3d577586fd
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
2019-04-10 16:15:23 -07:00
Eddie Hung
3f5dab0d09
Fix for when B_SIGNED = 1
2019-04-10 14:51:10 -07:00
Eddie Hung
32561332b2
Update doc for synth_xilinx
2019-04-10 14:48:58 -07:00
Eddie Hung
17a02df05c
ff_map.v after abc
2019-04-10 12:36:06 -07:00
Eddie Hung
1ec949d5ed
Tidy up
2019-04-10 09:02:42 -07:00
Eddie Hung
526aef9c2a
Move map_cells to before map_luts
2019-04-10 08:50:31 -07:00
Eddie Hung
e0b46eb4cb
WIP for $shiftx to wide mux
2019-04-10 08:49:55 -07:00
Eddie Hung
4dac9818bd
Update LUT delays
2019-04-10 08:49:39 -07:00
Eddie Hung
9a6da9a79a
synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
Eddie Hung
3e368593eb
Add cells.lut to techlibs/xilinx/
2019-04-09 14:33:37 -07:00
Eddie Hung
fd88ab5c83
synth_xilinx to call abc with -lut +/xilinx/cells.lut
2019-04-09 14:32:39 -07:00
Eddie Hung
b9e19071b8
Add delays to cells.box
2019-04-09 14:32:10 -07:00
Keith Rothman
e107ccdde8
Fix LUT6_2 definition.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 11:43:19 -07:00
Eddie Hung
f2042fc7c4
synth_xilinx with abc9 to use -box
2019-04-09 11:01:46 -07:00
Eddie Hung
2ae26b986c
Add techlibs/xilinx/cells.box
2019-04-09 10:58:58 -07:00
Eddie Hung
3fc474aa73
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-09 10:06:44 -07:00
Keith Rothman
5e0339855f
Add additional cells sim models for core 7-series primatives.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 09:01:53 -07:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
a5f33b5409
Move dffinit til after abc
2019-04-05 16:20:43 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
9758701574
Move techamp t:$_DFF_?N? to before abc call
2019-04-05 15:39:05 -07:00
Eddie Hung
23a6533e98
Retry
2019-04-05 15:31:54 -07:00
Eddie Hung
8b6085254a
Resolve @daveshah1 comment, update synth_xilinx help
2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
2019-04-05 14:43:06 -07:00
Eddie Hung
544843da71
techmap inside map_cells stage
2019-04-05 12:55:52 -07:00
Eddie Hung
7b7ddbdba7
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 08:13:34 -07:00
Eddie Hung
e3f20b17af
Missing techmap entry in help
2019-04-04 08:13:10 -07:00
Eddie Hung
2fb02247a7
Use soft-logic, not LUT3 instantiation
2019-04-04 08:10:40 -07:00
Eddie Hung
572603409c
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 07:54:42 -07:00
Eddie Hung
d9cb787391
synth_xilinx to map_cells before map_luts
2019-04-04 07:48:13 -07:00
Eddie Hung
77755b5a66
Cleanup comments
2019-04-04 07:41:40 -07:00
Eddie Hung
736e19f02d
t:$dff* -> t:$dff t:$dffe
2019-04-04 07:39:19 -07:00
Eddie Hung
0e2d929cea
-nosrl meant when -nobram
2019-04-03 08:28:07 -07:00
Eddie Hung
ff385a5ad0
Remove duplicate STARTUPE2
2019-04-03 08:14:09 -07:00
Eddie Hung
88630cd02c
Disable shregmap in synth_xilinx if -retime
2019-04-03 07:14:20 -07:00
Eddie Hung
f9fb05cf66
synth_xilinx to use shregmap with -minlen 3
2019-03-25 13:18:55 -07:00
Eddie Hung
46753cf89f
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 13:10:42 -07:00
David Shah
46f6a60d58
xilinx: Add keep attribute where appropriate
...
Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 13:57:17 +00:00
Eddie Hung
4cc6b3e942
Add '-nosrl' option to synth_xilinx
2019-03-21 15:04:44 -07:00
Eddie Hung
81c207fb9b
Fine tune cells_map.v
2019-03-20 10:55:14 -07:00
Eddie Hung
505e4c2d59
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00
Add support for variable length Xilinx SRL > 128
2019-03-19 17:44:33 -07:00
Eddie Hung
ae2a625d05
Restore original synth_xilinx commands
2019-03-19 16:14:08 -07:00
Eddie Hung
9156e18f92
Fix spacing
2019-03-19 16:12:32 -07:00
Eddie Hung
f239cb821e
Fix INIT for variable length SRs that have been bumped up one
2019-03-19 14:54:43 -07:00
Eddie Hung
24553326dd
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 13:11:30 -07:00
Clifford Wolf
fe1fb1336b
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-19 20:30:28 +01:00
Eddie Hung
fadeadb8c8
Only accept <128 for variable length, only if $shiftx exclusive
2019-03-16 08:51:13 -07:00
Eddie Hung
29a8d4745e
Cleanup synth_xilinx
2019-03-15 23:01:40 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Eddie Hung
e7ef7fa443
Reverse bits in INIT parameter for Xilinx, since MSB is shifted first
2019-03-14 09:38:42 -07:00
Eddie Hung
af5706c2a3
Misspell
2019-03-14 09:06:56 -07:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
...
This reverts commit 26ecbc1aee
.
2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Eddie Hung
79b4a275ce
Fix cells_map for SRL
2019-03-14 08:09:48 -07:00
Eddie Hung
edca2f1163
Move shregmap until after first techmap
2019-03-13 17:13:52 -07:00
Eddie Hung
24f129ddfb
Refactor $__SHREG__ in cells_map.v
2019-03-13 16:17:54 -07:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream
...
Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
Clifford Wolf
13844c7658
Use "write_edif -pvector bra" for Xilinx EDIF files
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 15:16:13 -08:00
Keith Rothman
228f132ec3
Revert BRAM WRITE_MODE changes.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-04 09:22:22 -08:00
Keith Rothman
3e16f75bc6
Revert FF models to include IS_x_INVERTED parameters.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb
Use singular for disabling of DRAM or BRAM inference.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8
Modify arguments to match existing style.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54
Changes required for VPR place and route synth_xilinx.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:02:27 -08:00
Eddie Hung
1da0909662
Remove SRL16/32 from cells_xtra
2019-02-28 13:56:45 -08:00
Eddie Hung
73ddab6960
Add SRL16 and SRL32 sim models
2019-02-28 13:56:22 -08:00
Eddie Hung
8aab7fe7e6
Fix SRL16/32 techmap off-by-one
2019-02-28 13:56:00 -08:00
Eddie Hung
fe4d6898de
synth_xilinx to call shregmap with enable support
2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0
synth_xilinx to use shregmap with -params too
2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a
synth_xilinx to now have shregmap call after dff2dffe
2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
2019-02-28 09:31:24 -08:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Eddie Hung
99a14b0e37
Add support for Xilinx PS7 block
2018-11-10 12:45:07 -08:00
Tim 'mithro' Ansell
b111ea1228
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
...
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
2018-10-08 16:52:12 -07:00
Clifford Wolf
5f1fea08d5
Add inout ports to cells_xtra.v
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-04 11:30:55 +02:00
Tim Ansell
ad975fb694
xilinx: Adding missing inout IO port to IOBUF
2018-10-03 16:38:32 -07:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
...
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
Clifford Wolf
6991c132b5
Add Xilinx RAM64X1D and RAM128X1D simulation models
2018-03-07 17:31:48 +01:00
Clifford Wolf
8a69759306
Add techlibs/xilinx/lut2lut.v
2017-07-10 12:09:05 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
ff5c61b120
Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
Clifford Wolf
a75f94ec4a
Run dffsr2dff in synth_xilinx
2016-02-13 08:20:19 +01:00
Clifford Wolf
17372d8abd
Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00
Clifford Wolf
864808992b
Bugfix in Xilinx LUT mapping
2015-10-30 13:58:03 +01:00
Clifford Wolf
f42218682d
Added examples/ top-level directory
2015-10-13 15:41:20 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
c475deec6c
Switched to Python 3
2015-08-22 09:59:33 +02:00
Clifford Wolf
9596fe74de
Another bugfix for ice40 and xilinx brams_init make rules
2015-08-16 21:39:34 +02:00
Clifford Wolf
aedcfd6fd3
Fixed Makefile rules for generated share files
2015-08-16 21:15:07 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
c329233f0d
Added output args to synth_ice40
2015-05-26 17:08:53 +02:00
Clifford Wolf
61512b6f41
Verific build fixes
2015-05-17 08:19:52 +02:00
Clifford Wolf
3481f46d1e
Improved xilinx "bram1" test
2015-04-09 17:12:12 +02:00
Clifford Wolf
7319951145
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
Clifford Wolf
229825e1b8
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 13:37:07 +02:00
Clifford Wolf
b00cad81d7
Towards DRAM support in Xilinx flow
2015-04-09 08:17:14 +02:00
Clifford Wolf
8520b7fbe0
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
Clifford Wolf
d19866615b
Added Xilinx test case for initialized brams
2015-04-06 13:27:11 +02:00
Clifford Wolf
4389d9306e
Added Xilinx bram black-box modules
2015-04-06 08:44:30 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
4d34d031f9
Added "stat" to "synth" and "synth_xilinx"
2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9
Added final checks to "synth" and "synth_xilinx"
2015-02-15 13:00:00 +01:00
Clifford Wolf
853e949c0e
Disabled (unused) Xilinx tristate buffers
2015-02-04 16:33:59 +01:00
Clifford Wolf
bebbf2e5a4
no support for 6-series xilinx devices
2015-02-01 23:06:44 +01:00
Clifford Wolf
3cbfa3815e
Removed old XST-based xilinx examples
2015-02-01 17:10:46 +01:00
Clifford Wolf
816fe6bbe0
Added Xilinx example for Basys3 board
2015-02-01 17:09:34 +01:00
Clifford Wolf
1b159bc955
Added missing ports and parameters to xilinx brams
2015-02-01 15:42:59 +01:00
Clifford Wolf
909a95182b
Fixed xilinx FDSE sim model
2015-01-24 11:03:22 +01:00
Clifford Wolf
d29d26f882
Various cleanups in xilinx techlib
2015-01-18 19:43:54 +01:00
Clifford Wolf
8d295730e5
Refactoring of memory_bram and xilinx brams
2015-01-18 19:05:29 +01:00
Clifford Wolf
279a18c9a3
Added synth_xilinx -retime -flatten
2015-01-17 20:47:18 +01:00
Clifford Wolf
7031231145
Added MUXCY and XORCY support to synth_xilinx
2015-01-17 15:39:54 +01:00
Clifford Wolf
dff8bd3b2a
Added dff2dffe to synth_xilinx
2015-01-16 15:49:15 +01:00
Clifford Wolf
7bde74cd2a
Added more FF types to xilinx/cells.v
2015-01-16 15:24:54 +01:00
Clifford Wolf
6b09153320
Fixed xilinx bram clock inverted config
2015-01-16 15:11:56 +01:00
Clifford Wolf
fd8c8d4fd3
Added FF cells to xilinx/cells_sim.v
2015-01-16 14:59:40 +01:00
Clifford Wolf
b197279f3c
Added Xilinx MUXF7 and MUXF8 support
2015-01-15 13:50:04 +01:00
Clifford Wolf
153d3dd4e0
Various cleanups in synth_xilinx command
2015-01-13 13:20:32 +01:00
Clifford Wolf
1d96277f5d
Added add_share_file Makefile macro
2015-01-08 00:23:18 +01:00
Clifford Wolf
38dfc5c580
added minimalistic xilinx sim models
2015-01-08 00:05:11 +01:00
Clifford Wolf
d1e38693d5
More Xilinx bram cleanups
2015-01-07 01:59:36 +01:00
Clifford Wolf
584c5f3937
Cleanups in xilinx bram descriptions
2015-01-07 01:28:18 +01:00
Clifford Wolf
08c13f635c
Xilinx RAMB36/RAMB18 memory_bram support complete
2015-01-06 23:54:33 +01:00
Clifford Wolf
ec2eef89fa
Towards Xilinx bram support
2015-01-06 23:21:52 +01:00
Clifford Wolf
7cc5192125
small fix in xilinx/brams.v
2015-01-06 17:21:18 +01:00
Clifford Wolf
9474928672
Towards Xilinx bram support
2015-01-06 15:26:33 +01:00
Clifford Wolf
4a0b3a5423
Various small improvements to synth_xilinx
2015-01-06 14:37:50 +01:00
Clifford Wolf
081e1a49f8
Towards Xilinx bram support
2015-01-06 14:26:51 +01:00
Clifford Wolf
9c7f47bbd5
Towards Xilinx bram support
2015-01-06 13:33:51 +01:00
Clifford Wolf
9ea2511fe8
Towards Xilinx bram support
2015-01-05 13:59:04 +01:00
Clifford Wolf
8898897f7b
Towards Xilinx bram support
2015-01-04 14:23:30 +01:00
Clifford Wolf
327a5d42b6
Progress in memory_bram
2014-12-31 22:50:08 +01:00
Clifford Wolf
94e6b70736
Added memory_bram (not functional yet)
2014-12-31 16:53:53 +01:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
20175afd29
Added "techmap -share_map" option
2013-11-24 19:50:25 +01:00
Clifford Wolf
ae798d3fd5
Fixed xilinx/example_sim_counter test bench
2013-11-24 17:55:46 +01:00
Clifford Wolf
532091afcb
Added more generic _TECHMAP_ wire mechanism to techmap pass
2013-11-23 15:58:06 +01:00
James Walmsley
40b3551b45
[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
...
Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
2013-10-27 21:48:39 +01:00
Clifford Wolf
88cd2eadf5
Cleanups in xilinx examples
2013-10-27 09:58:53 +01:00
Clifford Wolf
4a3669d871
Added synth_xilinx command
2013-10-27 09:51:06 +01:00
Clifford Wolf
90b016716b
Moved simple xilinx counter sim example to subdir
2013-10-27 09:30:17 +01:00
Clifford Wolf
02f321b6fc
Xilinx mojo_counter example is now working
2013-10-27 08:21:56 +01:00
Clifford Wolf
d635f8adaa
Renamed techlibs/xilinx7 to techlibs/xilinx
2013-10-26 22:29:40 +02:00