riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,335 Commits 89 Branches 49 Tags 38 MiB
Commit Graph

52 Commits

Author SHA1 Message Date
Clifford Wolf 3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
Clifford Wolf cae5131bac Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00