Claire Wolf
ffadaddab5
Merge pull request #1654 from YosysHQ/eddie/sby_fix69
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verific: unflatten struct ports
2020-01-30 18:03:35 +01:00
Claire Wolf
23c44afaed
Add Verific support for OPER_REDUCE_NAND
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-30 18:01:13 +01:00
Eddie Hung
6d27d43727
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
Eddie Hung
ce6a690d27
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
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Now done in read_aiger
2020-01-27 13:30:27 -08:00
Eddie Hung
f443695a38
Merge remote-tracking branch 'origin/master' into eddie/verific_help
2020-01-27 10:34:10 -08:00
Eddie Hung
d730bba6d2
verific: no help() when no YOSYS_ENABLE_VERIFIC
2020-01-27 10:32:18 -08:00
Eddie Hung
7b445121cc
verific: also unflatten for 'hierarchy' flow as per @cliffordwolf
2020-01-27 10:15:22 -08:00
Eddie Hung
c7fbe13db5
read_aiger: set abc9_box_seq attr
2020-01-24 13:11:43 -08:00
Eddie Hung
cccc0ae112
verific: unflatten struct ports
2020-01-24 10:12:52 -08:00
Eddie Hung
73526a6f10
read_aiger: also parse abc9_mergeability
2020-01-22 14:21:25 -08:00
Eddie Hung
cd093c00f8
read_aiger: discard LUT inputs with nodeID == 0; not < 2
2020-01-21 11:56:30 -08:00
Eddie Hung
7f728bc116
read_aiger: ignore constant inputs on LUTs
2020-01-21 11:16:50 -08:00
David Shah
22c967e35e
ast: Add support for $sformatf system function
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Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
Jeff Wang
98c6bd7630
fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6
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The if(str == node->str) is in fact necessary (otherwise causes generate
for in Multiplier_2D in tests/simple/multiplier.v to fail with error
message "Right hand side of 3rd expression of generate for-loop is not
constant!"). Note: in PeterCrozier's implementation, the break only
breaks out of the switch-case, not the outer for loop.
2020-01-17 02:07:42 -05:00
Jeff Wang
549deb6373
fix enum in generate blocks
2020-01-16 18:13:30 -05:00
Jeff Wang
41a0a93dcc
allow enums to be declared at toplevel scope
2020-01-16 18:13:14 -05:00
Jeff Wang
cc2236d0c0
lexer doesn't seem to return TOK_REG for logic anymore
2020-01-16 18:08:58 -05:00
Jeff Wang
5ddf84d430
allow enum typedefs
2020-01-16 17:17:42 -05:00
Jeff Wang
16ea4ea61a
partial rebase of PeterCrozier's enum work onto current master
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I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.
Original commit:
"Initial implementation of enum, typedef, import. Still a WIP."
881833aa73
2020-01-16 13:51:47 -05:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
05c8858a90
read_aiger: $lut prefix in front
2020-01-15 14:31:32 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Eddie Hung
f63f76c372
read_aiger: also rename "$0"
2020-01-14 09:01:53 -08:00
Eddie Hung
2c65e1abac
abc9: break SCC by setting (* keep *) on output wires
2020-01-13 21:45:27 -08:00
Eddie Hung
ee95fa959a
read_aiger: uniquify wires with $aiger<autoidx> prefix
2020-01-13 21:28:27 -08:00
Eddie Hung
766e16b525
read_aiger: make $and/$not/$lut the prefix not suffix
2020-01-13 17:34:37 -08:00
Eddie Hung
d979648b7a
read_aiger: more accurate debug message
2020-01-09 10:02:19 -08:00
Eddie Hung
943ea4bf9e
read_aiger: do not double-count outputs for flops
2020-01-09 08:55:36 -08:00
Eddie Hung
2ca8c10e7a
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-07 15:43:22 -08:00
Eddie Hung
2ac36031d4
read_aiger: consistency between ascii and binary; also name latches
2020-01-07 13:30:31 -08:00
Eddie Hung
8f5388ea5b
read_aiger fixes
2020-01-07 11:59:57 -08:00
Eddie Hung
b94cf0c126
read_aiger: connect identical signals together
2020-01-07 11:43:28 -08:00
Eddie Hung
baba33fbd3
read_aiger: cope with latches and POs with same name
2020-01-07 11:22:48 -08:00
Eddie Hung
738af17a26
read_aiger: default -clk_name to be empty
2020-01-07 11:21:45 -08:00
Eddie Hung
61a2a60595
read_aiger: do not process box connections, work standalone
2020-01-07 09:48:11 -08:00
Eddie Hung
b57f692a9e
read_aiger: consistency between ascii and binary
2020-01-07 09:32:34 -08:00
Eddie Hung
83616e7866
read_aiger: add -xaiger option
2020-01-06 12:43:29 -08:00
Eddie Hung
96db05aaef
parse_xaiger to not take box_lookup
2019-12-31 17:06:03 -08:00
Eddie Hung
e5ed8e8e21
parse_xaiger to reorder ports too
2019-12-31 16:50:22 -08:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531
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verilog: preserve size of $genval$-s in for loops
2019-12-19 12:21:33 -05:00
Clifford Wolf
22dd9f107c
Send people to symbioticeda.com instead of verific.com
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-18 13:06:34 +01:00
Eddie Hung
a6fdb9f5c1
aiger frontend to user shorter, $-prefixed, names
2019-12-17 15:50:01 -08:00
Eddie Hung
5f50e4f112
Cleanup xaiger, remove unnecessary complexity with inout
2019-12-17 15:45:26 -08:00
Eddie Hung
0875a07871
read_xaiger to cope with optional '\n' after 'c'
2019-12-17 15:45:26 -08:00
Eddie Hung
c0339bbbf1
Name inputs/outputs of aiger 'i%d' and 'o%d'
2019-12-13 16:21:09 -08:00
Rodrigo Alejandro Melo
e9dc2759c4
Fixed some missing "verilog_" in documentation
2019-12-13 10:17:05 -03:00
Eddie Hung
1ac1697e15
Stray log_dump
2019-12-11 16:59:00 -08:00
Eddie Hung
af36943cb9
Preserve size of $genval$-s in for loops
2019-12-11 16:52:37 -08:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
ab667d3d47
Call abc9 with "&write -n", and parse_xaiger() to cope
2019-12-06 16:35:57 -08:00
Eddie Hung
69d8c1386a
Do not connect undriven POs to 1'bx
2019-12-06 16:21:06 -08:00
Clifford Wolf
7dece7955e
Merge pull request #1551 from whitequark/manual-cell-operands
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Clarify semantics of comb cells, in particular shifts
2019-12-05 08:24:24 -08:00
whitequark
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
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Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
Marcin Kościelnicki
0ce22cea46
read_ilang: do bounds checking on bit indices
2019-11-27 22:24:39 +01:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Clifford Wolf
db323685a4
Add Verific support for SVA nexttime properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 16:11:56 +01:00
Clifford Wolf
e93e4a7a2c
Improve handling of verific primitives in "verific -import -V" mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 16:00:07 +01:00
Clifford Wolf
6af0d03fae
Add Verific SVA support for "always" properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 15:52:21 +01:00
David Shah
9e4801cca7
sv: Correct parsing of always_comb, always_ff and always_latch
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:27:19 +00:00
Eddie Hung
a576747483
Consistent log message, ignore 's' extension
2019-11-20 15:40:46 -08:00
Clifford Wolf
55bda2b2c6
Correctly treat empty modules as blackboxes in Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:56:31 +01:00
Clifford Wolf
f6ff311a1d
Do not rename VHDL entities to "entity(impl)" when they are top modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:54:10 +01:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Eddie Hung
e2819ce31c
Oops
2019-11-19 13:25:38 -08:00
Eddie Hung
84711f0e8c
Print help message for verific pass
2019-11-19 13:24:48 -08:00
Clifford Wolf
65f197e28f
Add check for valid macro names in macro definitions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-07 13:30:03 +01:00
Clifford Wolf
84982b3083
Improve naming scheme for (VHDL) modules imported from Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 12:13:50 +02:00
Clifford Wolf
d49c6b2cba
Add "verific -L"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 09:14:03 +02:00
Clifford Wolf
5025aab8c9
Add "verilog_defines -list" and "verilog_defines -reset"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 13:35:56 +02:00
Clifford Wolf
4033ff8c2e
Fix handling of "restrict" in Verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 12:39:28 +02:00
Clifford Wolf
71936209cf
Fix parsing of .cname BLIF statements
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 09:06:57 +02:00
Clifford Wolf
935d3e19e2
Add .blackbox support to blif front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 00:00:27 +02:00
Clifford Wolf
e84cedfae4
Use "(id)" instead of "id" for types as temporary hack
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-14 05:24:31 +02:00
Eddie Hung
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Miodrag Milanovic
c0b14cfea7
Fixes for MSVC build
2019-10-04 16:29:46 +02:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Clifford Wolf
468b8a5178
Merge pull request #1419 from YosysHQ/eddie/lazy_derive
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module->derive() to be lazy and not touch ast if already derived
2019-10-03 12:06:12 +02:00
David Shah
e46e8753c8
frontends/ast: code style
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:55:43 +01:00
David Shah
5501d9090a
sv: Fix typedefs in blocks
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
David Shah
8cc1bee33c
sv: Disambiguate interface ports
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
David Shah
c0bb47beca
sv: Fix memories of typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
497faf4ec0
sv: Add %expect
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
af25585170
sv: Add support for memories of a typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
30d2326030
sv: Add support for memory typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
e70e4afb60
sv: Fix typedefs in packages
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
c962951612
sv: Fix typedef parameters
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40
sv: Switch parser to glr, prep for typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
Miodrag Milanovic
c026579c20
Define environ, fixes #1424
2019-10-01 18:45:07 +02:00
Eddie Hung
f9bb335294
Cleanup $currQ from aigerparse
2019-09-30 16:36:42 -07:00
Eddie Hung
0a1af434e8
Fix for svinterfaces
2019-09-30 14:52:04 -07:00
Eddie Hung
08b55a20e3
module->derive() to be lazy and not touch ast if already derived
2019-09-30 14:11:01 -07:00
Eddie Hung
8684b58bed
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 12:29:35 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc
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rpc: new frontend
2019-09-30 17:38:20 +00:00
whitequark
99a7f39084
rpc: new frontend.
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A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.
Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
2019-09-30 15:53:11 +00:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Miodrag Milanovic
9e55b234b4
Fix reading aig files on windows
2019-09-29 15:40:37 +02:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Eddie Hung
c340fbfab2
Force $inout.out ports to begin with '$' to indicate internal
2019-09-23 21:58:04 -07:00
Clifford Wolf
8da0888bf6
Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 12:16:20 +02:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
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peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
Clifford Wolf
25b08b1afd
Fix handling of range selects on loop variables, fixes #1372
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-16 11:25:37 +02:00
Clifford Wolf
a67d63714b
Fix handling of z_digit "?" and fix optimization of cmp with "z"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-13 13:39:39 +02:00
Clifford Wolf
855e6a9b91
Fix lexing of integer literals without radix
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-13 10:19:58 +02:00
Clifford Wolf
7eb593829f
Fix lexing of integer literals, fixes #1364
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-12 09:43:32 +02:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival
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Allow arrival times of sequential outputs to be specified to abc9
2019-09-05 12:00:23 -07:00
Clifford Wolf
4b7202c9c2
Merge pull request #1350 from YosysHQ/clifford/fixsby59
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Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
2019-09-05 18:14:28 +02:00
Eddie Hung
ba629e6a28
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-04 15:36:07 -07:00
Eddie Hung
d3eea82bc2
Revert "parse_xaiger() to do "clean -purge""
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This reverts commit 5d16bf8316
.
2019-09-04 15:21:39 -07:00
Eddie Hung
d6a84a78a7
Merge remote-tracking branch 'origin/master' into eddie/deferred_top
2019-09-03 10:49:21 -07:00
Clifford Wolf
25e5fbac90
Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
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Fixes https://github.com/YosysHQ/SymbiYosys/issues/59
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-02 22:56:38 +02:00
Eddie Hung
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
Eddie Hung
5d16bf8316
parse_xaiger() to do "clean -purge"
2019-08-29 17:24:25 -07:00
Eddie Hung
83ffec26cb
Remove newline
2019-08-29 09:08:58 -07:00
Eddie Hung
6510297712
Restore non-deferred code, deferred case to ignore non constant attr
2019-08-29 09:02:10 -07:00
Eddie Hung
34ae29295d
read_verilog -defer should still populate module attributes
2019-08-28 19:59:09 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
fe1b2337fd
Do not propagate mem2reg attribute through to result
2019-08-22 16:57:59 -07:00
Eddie Hung
a6776ee35e
mem2reg to preserve user attributes and src
2019-08-21 13:36:01 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
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This reverts commit 091bf4a18b
.
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
be9e4f1b67
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Clifford Wolf
c25c1e742b
Merge pull request #1308 from jakobwenzel/real_params
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Handle real values when deriving ast modules
2019-08-20 11:37:26 +02:00
Eddie Hung
3f4886e7a3
Fix typo
2019-08-19 10:42:00 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
9bfe924e17
Set abc_flop and use it in toposort
2019-08-19 09:40:01 -07:00
Jakob Wenzel
24971fda87
handle real values when deriving ast modules
2019-08-19 14:17:36 +02:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
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Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
Clifford Wolf
27d59dc055
Fix erroneous ifndef-NDEBUG in verific.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:49:55 +02:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
6b156beda1
Remove unused variable
2019-08-16 13:35:39 -07:00
Eddie Hung
847c54088e
Change signature of parse_blif to take IdString
2019-08-15 10:26:24 -07:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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This reverts commit c851dc1310
, reversing
changes made to f54bf1631f
.
2019-08-12 12:06:45 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
4f81213165
Merge pull request #1261 from YosysHQ/clifford/verific_init
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Automatically prune init attributes in verific front-end
2019-08-10 09:47:25 +02:00
Eddie Hung
446dcb3ed3
Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
2019-08-09 09:17:35 -07:00
Eddie Hung
9776084eda
Allow whitebox modules to be overwritten
2019-08-07 16:40:24 -07:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00