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136 Commits 92 Branches 49 Tags 38 MiB
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15 Commits

Author SHA1 Message Date
Clifford Wolf 8cc1c87ab8 Reorganized TODOs 2013-03-24 11:23:54 +01:00
Clifford Wolf df9753d398 Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00
Johann Glaser 1d30c66a7f added a TODO 2013-03-18 22:06:53 +01:00
Johann Glaser 2192873daa added description of Makefile include files for build configuration 2013-03-18 19:26:35 +01:00
Clifford Wolf 71de666003 More TODOs in README 2013-03-18 15:05:15 +01:00
Johann Glaser bcae4aae6e corrected typos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:05:14 +01:00
Clifford Wolf 8a6b0a3520 Added help messages to ilang and verilog frontends 2013-03-01 08:03:00 +01:00
Clifford Wolf 7fccad92f7 Added more help messages 2013-03-01 00:36:19 +01:00
Clifford Wolf a5c4bf2161 Added help command to README (and some other README changes) 2013-02-28 14:17:57 +01:00
Clifford Wolf 99d73fe028 Added some additional TODO items 2013-02-27 10:36:17 +01:00
Clifford Wolf a77a5136af Fixed typo in README 2013-02-27 09:45:09 +01:00
Clifford Wolf aa7daadc0a Added copyright statement to readme file 2013-02-27 09:41:04 +01:00
Clifford Wolf 6d1502b948 Added support for "always @(*)" 2013-01-16 17:32:11 +01:00
Clifford Wolf a24086d1db Added "getting started" section to README 2013-01-06 14:40:15 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00