riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
8,353 Commits 89 Branches 49 Tags 38 MiB
Commit Graph

8353 Commits

Author SHA1 Message Date
Eddie Hung 736b96b186 Call submod once, more meaningful submod names, ignore largest domain 2019-11-22 23:16:15 -08:00
Eddie Hung 1851f4b488 Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 23:01:18 -08:00
Eddie Hung db2268703f
Merge pull request #1520 from pietrmar/fix-1463 
coolrunner2: remove spurious log_pop() call, fixes #1463
 2019-11-22 22:45:40 -08:00
Eddie Hung d223e11a72 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 22:28:35 -08:00
Eddie Hung 5cd3d3db0a Remove redundant flatten 2019-11-22 22:28:10 -08:00
Martin Pietryka 97b22413e5 coolrunner2: remove spurious log_pop() call, fixes #1463 
This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.

Signed-off-by: Martin Pietryka <martin@pietryka.at>
 2019-11-23 06:21:40 +01:00
Eddie Hung cba3073026 submod to bitty rather bussy, for bussy wires used as input and output 2019-11-22 20:53:58 -08:00
Eddie Hung 08f85e6438 Stray dump 2019-11-22 20:53:48 -08:00
Eddie Hung 900c806d4e Move clkpart into passes/hierarchy 2019-11-22 17:25:53 -08:00
Eddie Hung 2c5dfd802d Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 17:24:45 -08:00
Eddie Hung 8119383f81 Constant driven signals are also an input to submodules 2019-11-22 17:23:51 -08:00
Eddie Hung 4fdcf8f7d7 Add another test with constant driver 2019-11-22 17:23:34 -08:00
Eddie Hung 89a4a4d90f Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 17:04:33 -08:00
Eddie Hung 573396851a Oops 2019-11-22 17:03:30 -08:00
Eddie Hung bf7d36627e Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 17:00:35 -08:00
Eddie Hung 95af8f56e4 Only action if there is more than one clock domain 2019-11-22 17:00:11 -08:00
Eddie Hung 00d76f6cc4 Replace TODO 2019-11-22 16:58:08 -08:00
Eddie Hung 74ea438136 Add testcase for signal used as part input part output 2019-11-22 16:52:55 -08:00
Eddie Hung 81548d1ef9 write_xaiger back to working with whole modules only 2019-11-22 16:52:17 -08:00
Eddie Hung 0806b8e398 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 16:50:56 -08:00
Eddie Hung 8779faf789 Cleanup spacing 2019-11-22 16:50:09 -08:00
Eddie Hung 6a52897aee sigmap(wire) should inherit port_output status of POs 2019-11-22 16:48:11 -08:00
Eddie Hung 2ef2e2c040 Add testcase 2019-11-22 16:48:11 -08:00
Eddie Hung 698854955c Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:41:48 -08:00
Eddie Hung 84153288bb Brackets 2019-11-22 15:41:34 -08:00
Eddie Hung 3df191cec5 Entry in Makefile.inc 2019-11-22 15:41:23 -08:00
Eddie Hung bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Eddie Hung 450ad0e9ba Add to CHANGELOG 2019-11-22 15:35:51 -08:00
Eddie Hung 856a3dc98d New 'clkpart' to {,un}partition design according to clock/enable 2019-11-22 15:35:51 -08:00
Eddie Hung 2a54fa41c4 Merge branch 'master' of github.com:YosysHQ/yosys 2019-11-22 15:13:18 -08:00
Eddie Hung 8ef241c6f4 Revert "write_xaiger to not use module POs but only write outputs if driven" 
This reverts commit 0ab1e496dc.
 2019-11-22 13:24:28 -08:00
Eddie Hung c761fa49b7 Missing endmodule 2019-11-22 12:37:57 -08:00
Clifford Wolf c03b6a3e9c
Merge pull request #1517 from YosysHQ/clifford/optmem 
Add "opt_mem" pass
 2019-11-22 18:11:58 +01:00
Clifford Wolf caa3b21f8b
Merge pull request #1515 from YosysHQ/clifford/svastuff 
Add Verific/SVA support for "always" and "nexttime" properties
 2019-11-22 18:10:34 +01:00
Clifford Wolf 03fb92ed6f Add "opt_mem" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 17:45:22 +01:00
Clifford Wolf db323685a4 Add Verific support for SVA nexttime properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 16:11:56 +01:00
Clifford Wolf e93e4a7a2c Improve handling of verific primitives in "verific -import -V" mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 16:00:07 +01:00
Clifford Wolf 6af0d03fae Add Verific SVA support for "always" properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 15:52:21 +01:00
Clifford Wolf 72d2ef6fd0
Merge pull request #1511 from YosysHQ/dave/always 
sv: Error checking for always_comb, always_latch and always_ff
 2019-11-22 15:32:29 +01:00
Marcin Kościelnicki e110df9c48 gowin: Remove show command from tests. 2019-11-22 14:49:35 +01:00
Marcin Kościelnicki 1d098b7195 gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
David Shah b60f32c6ec Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-22 12:46:19 +00:00
Eddie Hung 6841e3b1c2 Another sloppy mistake! 2019-11-21 16:33:20 -08:00
Eddie Hung fe36275234 Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff 2019-11-21 16:32:52 -08:00
Eddie Hung 39fdcb892b async2sync -> clk2fflogic 2019-11-21 16:27:34 -08:00
Eddie Hung 0ab1e496dc write_xaiger to not use module POs but only write outputs if driven 2019-11-21 16:19:28 -08:00
Eddie Hung c4ec42ac38 When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ 
Since they should be captured downwards from the owning flop
 2019-11-21 16:17:03 -08:00
Eddie Hung 5a30e3ac3b Merge branch 'eddie/xaig_dff_adff' into xaig_dff 2019-11-21 16:15:25 -08:00
Eddie Hung 911a152b39 Add test 2019-11-21 16:13:28 -08:00
David Shah 49b670ca38 sv: Add tests for SV always types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 21:06:28 +00:00