William Speirs
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31267a1ae8
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Header changes so it will compile on VS
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2014-10-17 11:41:36 +02:00 |
Clifford Wolf
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0b9282a779
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Added make_temp_{file,dir}() and remove_directory() APIs
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2014-10-12 12:11:57 +02:00 |
Clifford Wolf
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b1596bc0e7
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Added run_command() api to replace system() and popen()
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2014-10-12 10:57:15 +02:00 |
Clifford Wolf
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0a651f112f
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Disabled vhdl2verilog command for win32 builds
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2014-10-11 10:46:19 +02:00 |
Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
Clifford Wolf
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19cff41eb4
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Changed frontend-api from FILE to std::istream
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2014-08-23 15:03:55 +02:00 |
Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
Clifford Wolf
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0f9ca49dc6
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Added passing of various options to vhdl2verilog
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2014-07-12 10:02:39 +02:00 |
Clifford Wolf
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91704a7853
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Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
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2014-03-11 14:24:24 +01:00 |
Clifford Wolf
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4d07f88258
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Fixed gcc compiler warning
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2014-03-06 16:37:19 +01:00 |
Clifford Wolf
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ef90236a5d
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Fixed vhdl2verilog temp dir name
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2014-03-01 17:48:15 +01:00 |
Clifford Wolf
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04999f4af0
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Fixed vhdl2verilog help message
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2014-03-01 17:47:19 +01:00 |
Clifford Wolf
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0a60f95224
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Added vhdl2verilog
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2014-02-21 18:59:49 +01:00 |