Clifford Wolf
1a260ce89b
Merge pull request #712 from mmicko/anlogic-support
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Initial support for Anlogic FPGA
2018-12-05 09:08:04 -08:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
ea4870b126
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
2018-12-05 16:30:37 +00:00
whitequark
1719aa88ac
Extract ice40_unlut pass from ice40_opt.
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Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
2018-12-05 16:30:24 +00:00
Diego H
819ca73096
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
Miodrag Milanovic
43030db5ff
Leave only real black box cells
2018-12-02 11:57:50 +01:00
Miodrag Milanovic
83bce9f59c
Initial support for Anlogic FPGA
2018-12-01 18:28:54 +01:00
Sylvain Munaut
3e5ab50a73
ice40: Add option to only use CE if it'd be use by more than X FFs
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
dbc4cb8f4a
Merge pull request #697 from eddiehung/xilinx_ps7
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Add support for PS7 block for Xilinx
2018-11-12 09:09:22 +01:00
Clifford Wolf
317cc9c2b7
Merge pull request #695 from daveshah1/ecp5_bb
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ecp5: Adding some blackbox cells
2018-11-12 09:08:49 +01:00
Eddie Hung
99a14b0e37
Add support for Xilinx PS7 block
2018-11-10 12:45:07 -08:00
David Shah
fae3e645a2
ecp5: Add 'fake' DCU parameters
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-09 18:25:42 +00:00
David Shah
960c8794fa
ecp5: Add blackboxes for ancillary DCU cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-09 15:18:30 +00:00
David Shah
1f51332808
ecp5: Adding some blackbox cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-07 14:56:38 +00:00
Clifford Wolf
d084fb4c3f
Fix sf2 LUT interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-31 15:36:53 +01:00
Clifford Wolf
cf79fd4376
Basic SmartFusion2 and IGLOO2 synthesis support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-31 15:28:57 +01:00
David Shah
b65932edc4
ecp5: Remove DSP parameters that don't work
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-22 16:20:38 +01:00
David Shah
101f5234ff
ecp5: Add DSP blackboxes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-21 19:27:02 +01:00
David Shah
d29b517fef
ecp5: Sim model fixes
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 15:16:40 +01:00
David Shah
677b8ed3ca
ecp5: Add latch inference
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 15:16:40 +01:00
Clifford Wolf
24a5c65856
Merge pull request #657 from mithro/xilinx-vpr
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xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
2018-10-18 10:54:03 +02:00
David Shah
df4bfa0ad6
ecp5: Disable LSR inversion
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-16 12:48:39 +01:00
David Shah
812538a036
BRAM improvements
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-12 14:22:21 +01:00
David Shah
bdfead8c64
ecp5: Adding BRAM maps for all size options
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 17:18:17 +01:00
David Shah
983fb7ff88
ecp5: First BRAM type maps successfully
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 16:35:19 +01:00
David Shah
2ef1af8b58
ecp5: Script for BRAM IO connections
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 16:11:00 +01:00
David Shah
346cbbdbdc
ecp5: Adding BRAM initialisation and config
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell
b111ea1228
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
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Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
2018-10-08 16:52:12 -07:00
David Shah
31e22c8b96
ecp5: Add blackbox for DP16KD
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-05 11:35:59 +01:00
Clifford Wolf
5f1fea08d5
Add inout ports to cells_xtra.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-04 11:30:55 +02:00
Tim Ansell
ad975fb694
xilinx: Adding missing inout IO port to IOBUF
2018-10-03 16:38:32 -07:00
Clifford Wolf
76baae4b94
Merge pull request #645 from daveshah1/ecp5_dram_fix
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ecp5: Don't map ROMs to DRAM
2018-10-02 10:00:10 +02:00
David Shah
fcd39e1398
ecp5: Don't map ROMs to DRAM
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-01 18:34:41 +01:00
Clifford Wolf
51f1bbeeb0
Add iCE40 SB_SPRAM256KA simulation model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-10 11:57:24 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
David Shah
3a3558acce
ecp5: Fixing miscellaneous sim model issues
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:56:12 +02:00
David Shah
e9ef077266
ecp5: Fixing 'X' issues with LUT simulation models
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:20:34 +02:00
David Shah
b2c62ff8ef
ecp5: ECP5 synthesis fixes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 14:33:13 +02:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
David Shah
241429abac
ecp5: Add DRAM match rule
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:25:52 +02:00
David Shah
4a60bc83ab
ecp5: Cells and mappings fixes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:14:08 +02:00
David Shah
b0fea67cc6
ecp5: Fixing arith_map
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:49:59 +02:00
David Shah
11c916840d
ecp5: Initial arith_map implementation
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:46:12 +02:00
David Shah
c2d7be140a
ecp5: Adding basic synth_ecp5 based on synth_ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:52:25 +02:00
David Shah
eb8f3f7dc4
ecp5: Adding DFF maps
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:32:23 +02:00
David Shah
1def34f2a6
ecp5: Adding DRAM map
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:08:42 +02:00
David Shah
b1b9e23f94
ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:27:24 +02:00
David Shah
cd65eeb3b3
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:09:18 +02:00
Clifford Wolf
57fc8dd582
Add "synth_ice40 -json"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-13 13:35:10 +02:00
Clifford Wolf
83631555dd
Fix ice40_opt for cases where a port is connected to a signal with width != 1
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-11 18:12:42 +02:00
Clifford Wolf
7fecc3c199
Make -nordff the default in "prep"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 13:17:09 +02:00
Olof Kindgren
faac2c5595
Avoid mixing module port declaration styles in ice40 cells_sim.v
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The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
2018-05-17 13:54:43 +02:00
Clifford Wolf
47eb150eec
Merge pull request #537 from mithro/yosys-vpr
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Improving Yosys when used with VPR
2018-05-04 12:32:30 +02:00
Clifford Wolf
b4c1d3084f
Add "synth_intel --noiopads"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-30 13:02:56 +02:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
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* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Tim 'mithro' Ansell
ca39e493ba
synth_ice40: Rework the vpr blif output slightly.
2018-04-18 16:55:08 -07:00
Clifford Wolf
81a457c4a6
Add "synth_ice40 -nodffe"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-16 20:44:26 +02:00
c60k28
efed2420d6
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
Robert Ou
14e49fb057
coolrunner2: Add an ANDTERM/XOR between chained FFs
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In some cases (e.g. the low bits of counters) the design might end up
with a flip-flop whose input is directly driven by another flip-flop.
This isn't possible in the Coolrunner-II architecture, so add a single
AND term and XOR in this case.
2018-03-31 03:54:48 -07:00
Robert Ou
cfa3753b89
coolrunner2: Split multi-bit nets
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The PAR tool doesn't expect any "dangling" nets with no drivers nor
sinks. By splitting the nets, clean removes them.
2018-03-31 02:56:11 -07:00
Robert Ou
8fe9cdf364
coolrunner2: Add extraction for TFFs
2018-03-31 02:54:26 -07:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
Clifford Wolf
6991c132b5
Add Xilinx RAM64X1D and RAM128X1D simulation models
2018-03-07 17:31:48 +01:00
Clifford Wolf
27dd500d31
Add "synth -noshare"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 17:13:45 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Robert Ou
2abcd98527
coolrunner2: Move LOC attributes onto the IO cells
2018-01-17 16:17:32 -08:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
b66d50e62d
Fix minor typo in "prep" help message
2017-12-19 21:44:05 +01:00
Graham Edgecombe
f93e6637aa
Fix port names in SB_IO_OD
2017-12-10 15:33:38 +00:00
Graham Edgecombe
52ace35a73
Remove trailing comma from SB_IO_OD port list
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This isn't compatible with Icarus Verilog.
2017-12-10 15:33:38 +00:00
Tim Ansell
3cc31f197c
Fix spelling in -vpr help for synth_ice40
2017-12-08 18:44:45 -08:00
Clifford Wolf
1f6e8f86c5
Merge pull request #462 from daveshah1/up5k
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Add remaining UltraPlus cells to ice40 techlib
2017-11-28 15:53:53 +01:00
David Shah
5e8d1922a4
Add remaining UltraPlus cells to ice40 techlib
2017-11-28 11:07:49 +00:00
Clifford Wolf
4782d59a3f
Merge pull request #455 from daveshah1/up5k
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Add UltraPlus specific cells to ice40 techlib
2017-11-18 19:12:48 +01:00
David Shah
0505f1043c
Remove unnecessary keep attributes
2017-11-18 17:53:21 +00:00
Clifford Wolf
c01df04e32
Merge pull request #453 from dh73/master
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Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
2017-11-18 09:56:36 +01:00
David Shah
8ae73e60e2
Merge branch 'master' into up5k
2017-11-17 15:15:39 +00:00
Clifford Wolf
234726c655
Add "synth_ice40 -vpr"
2017-11-16 21:37:02 +01:00
David Shah
f9f3ca5da0
Add some UltraPlus cells to ice40 techlib
2017-11-16 12:24:35 +00:00
dh73
3fd1d61e2a
Initial Cyclone 10 support
2017-11-08 22:45:21 -06:00
dh73
1fc061d90c
Organizing Speedster file names
2017-11-08 20:23:55 -06:00
Larry Doolittle
50bcd9a728
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
Clifford Wolf
65f91e5120
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
2017-10-03 17:31:21 +02:00
dh73
4718e65763
Tested and working altsyncarm without init files
2017-10-01 19:59:45 -05:00
dh73
cbaba62401
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00
Clifford Wolf
c5b204d8d2
Add first draft of eASIC back-end
2017-09-29 17:53:43 +02:00
Clifford Wolf
e64b9d5a4d
Fix synth_ice40 doc regarding -top default
2017-09-29 17:52:57 +02:00
Andrew Zonenberg
122532b7e1
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
Andrew Zonenberg
a84172b23b
Initial support for extraction of counters with clock enable
2017-09-14 10:26:10 -07:00
Clifford Wolf
2f75240e36
Merge pull request #406 from azonenberg/coolrunner-techmap
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Coolrunner techmapping improvements
2017-09-02 13:43:51 +02:00
Robert Ou
5f65e24ccb
coolrunner2: Finish fixing special-use p-terms
2017-09-01 07:22:16 -07:00
Robert Ou
fa04366f38
coolrunner2: Generate a feed-through AND term when necessary
2017-09-01 07:22:01 -07:00
Robert Ou
6775177171
coolrunner2: Initial fixes for special p-terms
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Certain signals can only be controlled by a product term and not a
sum-of-products. Do the initial work for fixing this.
2017-09-01 07:21:51 -07:00
Robert Ou
7f08be4304
coolrunner2: Fix mapping of flip-flops
2017-09-01 07:21:39 -07:00
Robert Ou
ac84f47829
coolrunner2: Combine some for loops together
2017-09-01 07:21:31 -07:00
Andrew Zonenberg
40021d2fd8
Fixed typo in error message
2017-09-01 06:45:10 -07:00
Andrew Zonenberg
fc0c7f74dc
Added blackbox $__COUNT_ cell model
2017-09-01 06:44:28 -07:00
Andrew Zonenberg
80aaf50302
Refactoring: moved modules still in cells_sim to cells_sim_wip
2017-09-01 06:44:15 -07:00
Andrew Zonenberg
06754108fc
Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction
2017-08-30 16:40:41 -07:00
Andrew Zonenberg
634f18be96
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
2017-08-30 16:28:25 -07:00