Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
Clifford Wolf
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2bec47a404
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Use only module->addCell() and module->remove() to create and delete cells
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2014-07-25 17:56:19 +02:00 |
Clifford Wolf
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4e802eb7f6
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Fixed all users of SigSpec::chunks_rw() and removed it
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2014-07-23 15:36:09 +02:00 |
Clifford Wolf
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28b3fd05fa
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
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2014-07-22 20:58:44 +02:00 |
Clifford Wolf
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4b4048bc5f
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SigSpec refactoring: using the accessor functions everywhere
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
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a233762a81
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SigSpec refactoring: renamed chunks and width to __chunks and __width
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
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361e0d62ff
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Replaced depricated NEW_WIRE macro with module->addWire() calls
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2014-07-21 12:42:02 +02:00 |
Clifford Wolf
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32a91458a7
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Added hilomap command
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2014-01-19 21:58:58 +01:00 |