riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,078 Commits 89 Branches 49 Tags 38 MiB
Commit Graph

10078 Commits

Author SHA1 Message Date
Clifford Wolf 973507d85b Fixes for improved techmap of shifts with large B inputs 2014-03-06 13:33:12 +01:00
Clifford Wolf 97710ffad5 Fixed use of frozen literals in SatGen 2014-03-06 13:08:44 +01:00
Clifford Wolf 8406e7f7b6 Strictly zero-extend unsigned A-inputs of shift operations in techmap 2014-03-06 12:15:44 +01:00
Clifford Wolf 1ecaf1bb76 Added techmap -max_iter option 2014-03-06 12:15:17 +01:00
Clifford Wolf d7f29bb23f Improved techmap of shift with wide B inputs 2014-03-06 12:14:20 +01:00
Clifford Wolf a1bfde8c5e Strictly zero-extend unsigned A-inputs of shift operations 2014-03-06 11:53:37 +01:00
Clifford Wolf b1b8fe3a56 Switched to EZMINISAT_SIMPSOLVER as default SAT solver 2014-03-05 19:57:10 +01:00
Clifford Wolf 09805ee9ec Include id2ast pointers when dumping AST 2014-03-05 19:56:31 +01:00
Clifford Wolf d6a01fe412 Fixed merging of compatible wire decls in AST frontend 2014-03-05 19:55:58 +01:00
Clifford Wolf de7bd12004 Bugfix in recursive AST simplification 2014-03-05 19:45:33 +01:00
Clifford Wolf 96e753041d fixed freduce for Minisat::SimpSolver: use frozen_literal() 2014-03-03 02:14:27 +01:00
Clifford Wolf d5bd93997c ezSAT: Added frozen_literal() API 2014-03-03 02:13:17 +01:00
Clifford Wolf 895e9fc70c ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressions 2014-03-03 02:12:45 +01:00
Clifford Wolf d500bd749f Added ezSAT::eliminated API to help the SAT solver remember eliminated variables 2014-03-01 21:00:34 +01:00
Clifford Wolf 23f0a12c72 ezSAT bugfix: don't call virtual methods in base class constructor 2014-03-01 20:59:00 +01:00
Clifford Wolf edc2146056 Removed ezSAT::assumed() API 2014-03-01 20:55:06 +01:00
Clifford Wolf e3debea4e6 Removed ezSAT built-in brute-froce solver 2014-03-01 20:53:09 +01:00
Clifford Wolf ef90236a5d Fixed vhdl2verilog temp dir name 2014-03-01 17:48:15 +01:00
Clifford Wolf 04999f4af0 Fixed vhdl2verilog help message 2014-03-01 17:47:19 +01:00
Clifford Wolf 9e99984336 Fixed const folding of $bu0 cells 2014-02-27 04:09:32 +01:00
Clifford Wolf ae5032af84 Fixed bit-extending in $mux argument (use $bu0 instead of $pos) 2014-02-26 21:32:19 +01:00
Clifford Wolf aaaa604853 Added support for $bu0 to SatGen 2014-02-26 21:31:34 +01:00
Clifford Wolf 6bc94b7eb2 Don't blow up constants unneccessarily in Verilog frontend 2014-02-24 12:41:25 +01:00
Clifford Wolf dab1612f81 Added support for Minisat::SimpSolver + ezSAT frezze() API 2014-02-23 01:35:59 +01:00
Clifford Wolf b76528d8a5 Fixed small memory leak in Pass::call() 2014-02-23 01:28:29 +01:00
Clifford Wolf f8c9143b2b Fixed bug in generation of undefs for $memwr MUXes 2014-02-22 17:08:00 +01:00
Clifford Wolf 548519875b Fixed bug (typo) in passes/opt/opt_const.cc 2014-02-22 17:07:22 +01:00
Clifford Wolf 337b461d26 Added $lut support to blif backend (by user eddiehung from reddit) 2014-02-22 14:25:32 +01:00
Clifford Wolf 357f3f6e93 Added ezMiniSat EZMINISAT_INCREMENTAL compile-time option 2014-02-22 11:34:31 +01:00
Clifford Wolf 1ec01d8c63 Made MiniSat solver backend configurable in ezminisat.h 2014-02-22 01:29:02 +01:00
Clifford Wolf 8b508dc90b Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst 2014-02-21 23:34:45 +01:00
Clifford Wolf 0a60f95224 Added vhdl2verilog 2014-02-21 18:59:49 +01:00
Clifford Wolf 79edcd4318 Progress in presentation 2014-02-21 14:59:59 +01:00
Clifford Wolf 038eac7414 Better handling of nameDef and nameRef in edif backend 2014-02-21 13:40:43 +01:00
Clifford Wolf f3ff29d410 Fixed instantiating multi-bit ports in edif backend 2014-02-21 13:10:36 +01:00
Clifford Wolf 3c5e973092 Use private namespace in mem_simple_4x1_map 2014-02-21 12:14:38 +01:00
Clifford Wolf 81b3f52519 Added tests/techmap/mem_simple_4x1 2014-02-21 12:06:40 +01:00
Clifford Wolf 79f8944811 Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param 2014-02-21 10:40:15 +01:00
Clifford Wolf 2aff7b2a47 Progress in presentation 2014-02-21 02:13:02 +01:00
Clifford Wolf 9351e4d3ca Progress in presentation 2014-02-20 23:44:28 +01:00
Clifford Wolf 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap 2014-02-20 23:42:07 +01:00
Clifford Wolf 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." 2014-02-20 23:31:13 +01:00
Clifford Wolf 236fc4209c Added "extract -map %<design_name>" 2014-02-20 23:30:15 +01:00
Clifford Wolf 483c99fe46 Added "design -push" and "design -pop" 2014-02-20 23:28:59 +01:00
Clifford Wolf b0e84802ec Progress in presentation 2014-02-20 20:44:41 +01:00
Clifford Wolf 0dadfed46d Added connwrappers command 2014-02-20 20:44:11 +01:00
Clifford Wolf 4bd25edcd4 Cleanups in handling of read_verilog -defer and -icells 2014-02-20 19:12:32 +01:00
Clifford Wolf 98940260e1 Progress in presentation 2014-02-20 12:46:29 +01:00
Clifford Wolf 772330608a Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...) 2014-02-19 12:40:49 +01:00
Clifford Wolf 23a3b488a0 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-18 20:05:53 +01:00