Eddie Hung
a682a3cf93
write_xaiger to support part-selected modules again
2019-12-05 17:54:43 -08:00
Eddie Hung
c6ee2fb482
Cleanup
2019-12-03 19:21:47 -08:00
Eddie Hung
df52bc80d8
write_xaiger to consume abc9_init attribute for abc9_flops
2019-12-03 18:47:44 -08:00
Eddie Hung
419ca5c207
Revert "Fold loop"
...
This reverts commit a30d5e1cc3
.
2019-11-27 21:55:56 -08:00
Eddie Hung
449b1d2c6f
Add comment, use sigmap
2019-11-27 13:20:12 -08:00
Eddie Hung
403214f44d
Revert "Fold loop"
...
This reverts commit da51492dbc
.
2019-11-27 12:35:25 -08:00
Eddie Hung
5e67df38ed
latch -> box
2019-11-26 22:59:05 -08:00
Eddie Hung
a30d5e1cc3
Fold loop
2019-11-26 21:57:50 -08:00
Eddie Hung
68717dd03b
Do not sigmap keep bits inside write_xaiger
2019-11-26 21:57:50 -08:00
Eddie Hung
7136cee6b4
xaiger: do not promote output wires
2019-11-26 21:55:37 -08:00
Eddie Hung
99702efaba
xaiger: do not promote output wires
2019-11-26 19:03:02 -08:00
Eddie Hung
da51492dbc
Fold loop
2019-11-25 15:43:37 -08:00
Eddie Hung
7f0914a408
Do not sigmap keep bits inside write_xaiger
2019-11-25 15:42:07 -08:00
Eddie Hung
81548d1ef9
write_xaiger back to working with whole modules only
2019-11-22 16:52:17 -08:00
Eddie Hung
8ef241c6f4
Revert "write_xaiger to not use module POs but only write outputs if driven"
...
This reverts commit 0ab1e496dc
.
2019-11-22 13:24:28 -08:00
Eddie Hung
0ab1e496dc
write_xaiger to not use module POs but only write outputs if driven
2019-11-21 16:19:28 -08:00
Eddie Hung
929beda19c
abc9 to support async flops $_DFF_[NP][NP][01]_
2019-11-19 16:57:26 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
whitequark
3c643c57df
write_verilog: add -extmem option, to write split memory init files.
...
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
2019-11-18 01:27:21 +00:00
Clifford Wolf
cd44826d50
Use cell name for btor bad state props when it is a public name
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-14 11:57:38 +01:00
Makai Mann
d88cc139a0
Add an info string symbol for bad states in btor backend
2019-11-11 16:40:51 -08:00
Clifford Wolf
5110a34dd7
Fix write_aiger bug added in 524af21
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-04 14:25:13 +01:00
Clifford Wolf
81876a3734
Merge pull request #1393 from whitequark/write_verilog-avoid-init
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write_verilog: do not print (*init*) attributes on regs
2019-10-27 10:25:01 +01:00
Clifford Wolf
f02623abb5
Bugfix in smtio vcd handling of $-identifiers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-23 00:04:34 +02:00
Eddie Hung
b2e34f932a
Rename $currQ to $abc9_currQ
2019-10-07 15:31:43 -07:00
Eddie Hung
90a954bb9c
Get rid of latch_* in write_xaiger
2019-10-07 13:09:13 -07:00
Eddie Hung
1504ca2cd9
Remove "write_xaiger -zinit"
2019-10-07 11:58:49 -07:00
Eddie Hung
e1554b56dd
Add comment on default flop init
2019-10-07 11:56:17 -07:00
Eddie Hung
d9fba95177
Get rid of output_port lookup
2019-10-07 11:49:06 -07:00
Eddie Hung
3879ca1398
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
Eddie Hung
3c6e5d82a6
Error if $currQ not found
2019-10-05 09:06:13 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Clifford Wolf
2ed2e9c3e8
Change smtbmc "Warmup failed" status to "PREUNSAT"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-03 14:59:07 +02:00
Clifford Wolf
a84a2d74c7
Fix btor back-end to use "state" instead of "input" for undef init bits
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-02 12:48:04 +02:00
Eddie Hung
1b96d29174
No need to punch ports at all
2019-09-30 17:02:20 -07:00
Eddie Hung
e529872b01
Remove need for $currQ port connection
2019-09-30 16:33:40 -07:00
Eddie Hung
eecfdda614
Cleanup
2019-09-30 15:24:03 -07:00
Eddie Hung
74678227c7
Use a cell_cache to instantiate once rather than opt_merge call
2019-09-30 13:21:07 -07:00
Eddie Hung
a6994c5f16
scc call on active module module only, plus cleanup
2019-09-30 12:57:19 -07:00
Eddie Hung
bd8356799a
Use derived module
2019-09-30 12:34:28 -07:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
f3e150d9a5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 09:21:51 -07:00
Miodrag Milanović
ce0631c371
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out
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Support binary files for backends, fixes #1407
2019-09-29 10:37:34 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Miodrag Milanovic
0c380f0855
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
Miodrag Milanovic
d0493925ec
Support binary files for backends, fixes #1407
2019-09-28 09:36:18 +02:00
Eddie Hung
cfa6dd61ef
Use abc_mergeability attr for "r" extension
2019-09-27 18:41:43 -07:00
Eddie Hung
dc154c39a8
Fix infinite recursion
2019-09-27 17:45:49 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Aman Goel
5eebfabe42
Corrects btor2 backend
2019-09-27 12:40:17 -04:00
Eddie Hung
44374b1b2b
"abc_padding" attr for blackbox outputs that were padded, remove them later
2019-09-23 21:58:40 -07:00
Eddie Hung
c340fbfab2
Force $inout.out ports to begin with '$' to indicate internal
2019-09-23 21:58:04 -07:00
whitequark
4f426c2ac4
write_verilog: do not print (*init*) attributes on regs.
...
If an init value is emitted for a reg, an (*init*) attribute is never
necessary, since it is exactly equivalent. On the other hand, some
tools that consume Verilog (ISE, Vivado, Quartus) complain about
(*init*) attributes because their interpretation differs from Yosys.
All (*init*) attributes that would not become reg init values anyway
are emitted as before.
2019-09-22 16:52:06 +00:00
Eddie Hung
2d9484c12c
When two boxes connect to each other, need not be a (* keep *)
2019-09-19 15:40:28 -07:00
Clifford Wolf
779ce3537f
Add "write_aiger -L"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-18 13:33:02 +02:00
Clifford Wolf
b88d2e5f30
Fix stupid bug in btor back-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-18 11:56:14 +02:00
Sean Cross
c1b628508d
backends: smt2: use $(CXX) variable for compiler
...
The Makefile assumes the compiler is called `gcc`, which isn't always
true. In fact, if we're building on msys2 or msys2-64, the compiler
is called `i686-w64-mingw32-g++` or `x86_64-w64-mingw32-g++`.
Use the variable instead of hardcoding the name, to fix building on
these systems.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-08 15:47:09 +08:00
Eddie Hung
e9bb252e77
Recognise built-in types (e.g. $_DFF_*)
2019-08-30 20:15:09 -07:00
Eddie Hung
3247442bf9
Revert "Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)""
...
This reverts commit 8f0c1232d7
.
2019-08-28 17:34:00 -07:00
Eddie Hung
082a01954b
Revert "Output "h" extension only if boxes"
...
This reverts commit 399ac760ff
.
2019-08-28 17:30:54 -07:00
Eddie Hung
399ac760ff
Output "h" extension only if boxes
2019-08-21 11:31:18 -07:00
Eddie Hung
8f0c1232d7
Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)"
...
This reverts commit 8182cb9d91
.
2019-08-21 11:29:40 -07:00
Eddie Hung
8182cb9d91
Fix omode which inserts an output if none exists (otherwise abc9 breaks)
2019-08-20 21:30:16 -07:00
Eddie Hung
4d123b7638
Revert "Only xaig if GetSize(output_bits) > 0"
...
This reverts commit 7b646101e9
.
2019-08-20 21:22:38 -07:00
Eddie Hung
7b646101e9
Only xaig if GetSize(output_bits) > 0
2019-08-20 20:57:13 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
...
This reverts commit 091bf4a18b
.
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
1b5d2de1d4
Do not sigmap!
2019-08-20 15:23:26 -07:00
Eddie Hung
c00d72cdb3
Minor refactor
2019-08-20 14:47:58 -07:00
Eddie Hung
45d4b33f0c
Output i/o/h extensions even if no boxes or flops
2019-08-19 13:17:31 -07:00
Eddie Hung
91687d3fea
Add (* abc_arrival *) attribute
2019-08-19 12:33:24 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
10c69f71e9
Use %d
2019-08-19 09:16:20 -07:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
4fe307f1bc
Compute abc_scc_break and move CI/CO outside of each abc9
2019-08-16 15:41:17 -07:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
05c46a31dc
Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell
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FIRRTL error on unsupported cell
2019-08-10 09:47:10 +02:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Jim Lawson
5e8a98c8fd
Merge branch 'master' into firrtl_err_on_unsupported_cell
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# Conflicts:
# backends/firrtl/firrtl.cc
2019-08-07 10:14:45 -07:00
Eddie Hung
3090da2d98
Run "clean -purge" on holes_module in its own design
2019-08-07 09:54:27 -07:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
2019-08-07 12:31:32 +02:00
David Shah
dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix
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Improved JSON attr/param encoding
2019-08-07 10:40:38 +01:00
Eddie Hung
e38f40af5b
Use IdString::begins_with()
2019-08-06 16:42:25 -07:00
Eddie Hung
a6bc9265fb
RTLIL::S{0,1} -> State::S{0,1}
2019-08-06 16:23:37 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Clifford Wolf
0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix
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Visual Studio build fix
2019-08-02 17:07:39 +02:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Clifford Wolf
15fae357f6
Implement improved JSON attr/param encoding
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-01 12:34:52 +02:00
Jim Lawson
3b8c917025
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
...
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
2019-07-31 09:27:38 -07:00
Miodrag Milanovic
35d28de478
Visual Studio build fix
2019-07-31 09:10:24 +02:00
Jim Lawson
7e298084e4
Call log_error() instead of log_warning() on unsupported cell type in FIRRTL backend.
2019-07-24 13:33:16 -07:00
Clifford Wolf
927f0caa9d
Merge pull request #1203 from whitequark/write_verilog-zero-width-values
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write_verilog: dump zero width constants correctly
2019-07-18 15:31:27 +02:00
Clifford Wolf
56c00e871f
Remove old $pmux_safe code from write_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-17 11:49:04 +02:00
whitequark
4ff44d85a5
write_verilog: dump zero width constants correctly.
...
Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.
After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)
Fixes #948 (again).
2019-07-16 21:00:09 +00:00
N. Engelhardt
ab4b9e8db4
smt: handle failure of setrlimit syscall
2019-07-15 23:33:18 +08:00
Clifford Wolf
9112850800
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
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write_verilog: write RTLIL::Sa aka - as Verilog ?
2019-07-11 07:25:52 +02:00
Eddie Hung
375fcbe511
abc_flop to also get topologically sorted
2019-07-10 20:26:09 -07:00
Eddie Hung
ea6ffea2cd
Fix clk_pol for FD*_1
2019-07-10 20:10:20 -07:00
Eddie Hung
e603d719d6
Fix spacing
2019-07-10 19:04:22 -07:00
Eddie Hung
4a995c5d80
Change how to specify flops to ABC again
2019-07-10 17:54:56 -07:00
Eddie Hung
a092c48f03
Use split_tokens()
2019-07-10 17:34:51 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
Clifford Wolf
6dd33be7ce
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
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write_verilog: fix placement of case attributes
2019-07-09 22:51:25 +02:00
whitequark
37bb6b5e96
write_verilog: fix placement of case attributes. NFC.
2019-07-09 19:14:03 +00:00
whitequark
6a29e1f5b7
write_verilog: write RTLIL::Sa aka - as Verilog ?.
...
Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
2019-07-09 18:35:49 +00:00
Eddie Hung
00d8a9dce2
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore
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Rename __builtin_bswap32 -> bswap32
2019-07-09 10:22:57 -07:00
Eddie Hung
5a0f2e43c7
Rename __builtin_bswap32 -> bswap32
2019-07-09 09:35:09 -07:00
whitequark
628437b01c
verilog_backend: dump attributes on SwitchRule.
...
This appears to be an omission.
2019-07-08 15:11:29 +00:00
whitequark
55c1f40277
verilog_backend: dump attributes on CaseRule, as comments.
...
Attributes are not permitted in that position by Verilog grammar.
2019-07-08 12:48:50 +00:00
whitequark
93bc5affd3
Allow attributes on individual switch cases in RTLIL.
...
The parser changes are slightly awkward. Consider the following IL:
process $0
<point 1>
switch \foo
<point 2>
case 1'1
assign \bar \baz
<point 3>
...
case
end
end
Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.
To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.
Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
Eddie Hung
10524064e9
write_xaiger to treat unknown cell connections as keep-s
2019-07-02 19:14:30 -07:00
Eddie Hung
69f4c039ce
Safe side: all flops have different mergeability class
2019-07-02 12:21:03 -07:00
Eddie Hung
a31e17182d
Refactor and cope with new abc_flop format
2019-07-01 11:50:34 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Eddie Hung
38d8806bd7
Add generic __builtin_bswap32 function
2019-06-28 09:59:47 -07:00
Eddie Hung
524af21317
Also fix write_aiger for UB
2019-06-28 09:55:07 -07:00
Eddie Hung
36e2eb06bb
Fix more potential for undefined behaviour due to container invalidation
2019-06-28 09:51:43 -07:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
080a5ca536
Improve debugging message for comb loops
2019-06-26 20:02:38 -07:00
Eddie Hung
cec2292b0b
Merge remote-tracking branch 'origin/master' into xaig
2019-06-24 20:01:43 -07:00
Eddie Hung
7903ebe3e0
Carry in/out box ordering now move to end, not swap with end
2019-06-22 14:18:42 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
fddb027cab
Replace assert with error message
2019-06-21 17:18:04 -07:00
Eddie Hung
7074ec9cd5
Add log_push()/log_pop() inside write_xaiger
2019-06-21 17:17:29 -07:00
Eddie Hung
65c1199acd
One more workaround for gcc-4.8
2019-06-21 14:36:24 -07:00
Eddie Hung
bd7ec673dd
No point logging constant bit
2019-06-21 14:31:09 -07:00
Eddie Hung
70c93ea0c4
Move comment
2019-06-21 14:31:09 -07:00
Miodrag Milanovic
fde90f7f8e
Fix json formatting
2019-06-21 20:01:40 +02:00
Miodrag Milanovic
50e7221077
Add upto and offset to JSON ports
2019-06-21 19:47:25 +02:00
Clifford Wolf
f15def325c
Added JSON upto and offset
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 15:22:17 +02:00
Eddie Hung
6a336ca23e
Fix spacing
2019-06-20 22:30:20 -07:00
Eddie Hung
e21f01d938
Refactor bit2aig for less lookups
2019-06-20 22:10:43 -07:00
Eddie Hung
4422b7311b
Fix gcc invalidation behaviour for write_aiger
2019-06-20 22:10:43 -07:00
Eddie Hung
32f8014e12
Fix gcc error, due to dict invalidation during recursion
2019-06-20 22:10:43 -07:00
Eddie Hung
c4ea6fff65
Fix gcc invalidation behaviour for write_aiger
2019-06-20 21:56:47 -07:00
Eddie Hung
8e56cfb6bb
write_xaiger to flatten 1'bx/1'bz to 1'b0 again
2019-06-20 19:41:27 -07:00
Eddie Hung
ad36eb24c0
Fix different abc9 test
2019-06-20 19:41:27 -07:00
Eddie Hung
9faeba7a66
Fix broken abc9.v test due to inout being 1'bx
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
4e5836a5fb
Handle COs driven by 1'bx
2019-06-20 17:38:04 -07:00