yosys

Commit Graph

Author	SHA1	Message	Date
Jannis Harder	331ac5285f	tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.	2024-02-01 16:14:11 +01:00
Clifford Wolf	482d9208aa	Added read_verilog -sv options, added support for bit, logic, allways_ff, always_comb, and always_latch	2014-06-12 11:54:20 +02:00
Clifford Wolf	7a66b38c3e	Added test cases for sat command	2014-02-04 13:43:34 +01:00

Author

SHA1

Message

Date

Jannis Harder

331ac5285f

tests: Run async2sync before sat and/or sim to handle $check cells

Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.

2024-02-01 16:14:11 +01:00

Clifford Wolf

482d9208aa

Added read_verilog -sv options, added support for bit, logic,

allways_ff, always_comb, and always_latch

2014-06-12 11:54:20 +02:00

Clifford Wolf

7a66b38c3e

Added test cases for sat command

2014-02-04 13:43:34 +01:00

3 Commits