Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Clifford Wolf
1b49380f6b
Improve BTOR2 handling of undriven wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 17:42:00 +02:00
Clifford Wolf
b7dd7c2dcd
Add proper error message for btor recursion_guard
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-24 16:22:34 +02:00
Clifford Wolf
148caecca3
Change "ne" to "neq" in btor2 output
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we need to do this because they changed the parser:
e97fc9ceda
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-19 21:17:12 +02:00
Clifford Wolf
1eff8be8f0
Add support for memory initialization to write_btor
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:40:01 +01:00
Clifford Wolf
e78f5a3055
Fix BTOR output tags syntax in writye_btor
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:39:42 +01:00
Clifford Wolf
23bb77867f
Minor style fixes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 20:02:39 +01:00
makaimann
abf5930a33
Add btor ops for $mul, $div, $mod and $concat
2018-12-17 10:45:17 -08:00
Clifford Wolf
ed3c57fad3
Fix btor init value handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-08 06:21:31 +01:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
9804ebedbf
Add "no driver for signal bit" error msg to btor back-end
2017-12-24 17:30:36 +01:00
Clifford Wolf
292984896b
Simple fix BTOR memory encoding
2017-12-17 18:57:54 +01:00
Clifford Wolf
bbdcc1f9d4
Improve BTOR memory encoding
2017-12-17 18:55:17 +01:00
Clifford Wolf
30f23281ed
Add array support to btor back-end
2017-12-15 02:19:06 +01:00
Clifford Wolf
ad901671c5
Add $anyconst/$anyseq support to btor back-end
2017-12-15 00:40:24 +01:00
Clifford Wolf
546de7fa4f
Add "write_btor -s" mode
2017-12-13 00:15:44 +01:00
Clifford Wolf
0881bbf2e7
Add state initval handling to btor back-end
2017-12-12 23:44:08 +01:00
Clifford Wolf
f697282246
Add btor back-end support for 'x' constants
2017-12-12 21:48:55 +01:00
Clifford Wolf
82d1fd77de
Add btor $shift/$shiftx support
2017-12-11 14:24:19 +01:00
Clifford Wolf
cc119b5232
Fix btor back-end shift handling
2017-12-10 08:40:11 +01:00
Clifford Wolf
133a0f4978
Add support for $pmux in btor back-end
2017-12-10 08:11:08 +01:00
Clifford Wolf
83cf736309
Add support for more cell types to btor back-end
2017-12-10 07:16:47 +01:00
Clifford Wolf
63343aeaaa
Fix btor concat
2017-12-09 05:58:14 +01:00
Clifford Wolf
e3a51b3e87
Bugfixes in new BTOR back-end
2017-11-24 18:13:41 +01:00
Clifford Wolf
60d1129506
Progress in new BTOR back-end
2017-11-23 23:44:39 +01:00
Clifford Wolf
b3d6b277ea
Progress in new BTOR back-end
2017-11-23 18:50:10 +01:00
Clifford Wolf
cc2495d48d
Progress in new BTOR back-end
2017-11-23 18:14:53 +01:00
Clifford Wolf
e41dcaa759
Progress with new BTOR backend
2017-11-23 08:28:29 +01:00
Clifford Wolf
6ee305553a
Add skeleton for new BTOR back-end
2017-11-23 06:38:57 +01:00
Clifford Wolf
eceacdb9a3
Remove old BTOR back-end
2017-11-23 04:28:51 +01:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
1d0f0d668a
Renamed opt_const to opt_expr
2016-03-31 08:46:56 +02:00
Clifford Wolf
0d7fd2585e
Added "int ceil_log2(int)" function
2016-02-13 16:52:16 +01:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
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Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
6834461f65
Remove some very strange whitespace in btor.cc (by Larry Doolittle)
2015-08-05 22:11:26 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
4c733301e6
Fixed cstr_buf for std::string with small string optimization
2015-06-11 13:39:49 +02:00
Clifford Wolf
aa0ab975b9
Removed "techmap -share_map" (use "-map +/filename" instead)
2015-04-08 12:13:53 +02:00
Ahmed Irfan
13e2e71ebe
Update README
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corrected url
2015-04-03 17:11:45 +02:00
Ahmed Irfan
ed750f0a55
Delete btor.ys
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.ys script not needed
2015-04-03 16:45:54 +02:00
Ahmed Irfan
e82e4f7df4
Update README
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pmux cell is implemented
2015-04-03 16:45:14 +02:00
Ahmed Irfan
ea2e0297d5
separated memory next from write cell
2015-04-03 16:41:50 +02:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Ahmed Irfan
d3c67ad9b6
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
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added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation
Conflicts:
backends/btor/btor.cc
2014-09-22 11:35:04 +02:00
ahmedirfan1983
b783dbe148
fixed memory next issue, when same memory is written in different case statement
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fixed reduce_xnor, logic_not bug translation bug
2014-09-18 11:19:48 +02:00
Ahmed Irfan
2446b6fbef
added $pmux cell translation
2014-09-02 14:47:51 +02:00
Clifford Wolf
e07698818d
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
2014-09-01 11:36:02 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
04727c7e0f
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
3f4e3ca8ad
More RTLIL::Cell API usage cleanups
2014-07-26 16:14:02 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
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git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
5826670009
Various RTLIL::SigSpec related code cleanups
2014-07-25 14:25:42 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
f7bd0a5232
Use log_abort() and log_assert() in BTOR backend
2014-03-07 15:56:10 +01:00
Ahmed Irfan
ac896c63e2
modified btor synthesis script for correct use of splice command.
2014-02-12 13:38:28 +01:00
Ahmed Irfan
45e468114a
disabling splice command in the script
2014-02-11 15:43:03 +01:00
Ahmed Irfan
1d64b3e008
register output corrected
2014-02-11 13:28:05 +01:00
Ahmed Irfan
e8f6b8f201
added concat and slice cell translation
2014-02-11 13:06:01 +01:00
Clifford Wolf
f4f230d7cc
Fixed gcc compiler warnings with release build
2014-02-06 22:49:14 +01:00
Clifford Wolf
583636f0ad
Added BTOR backend README file
2014-02-05 18:31:10 +01:00
Clifford Wolf
a6750b3753
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
Ahmed Irfan
0325efe172
root bug corrected
2014-01-25 19:33:24 +01:00
Ahmed Irfan
137742786e
removed regex include
2014-01-24 18:04:37 +01:00
Ahmed Irfan
2e44b1b73a
merged clifford changes + removed regex
2014-01-24 17:35:42 +01:00
Clifford Wolf
210dda286f
Use techmap -share_map in btor scripts
2014-01-24 15:52:16 +01:00
Clifford Wolf
6804edd5d4
Moved btor scripts to backends/btor/
2014-01-24 15:48:07 +01:00
Ahmed Irfan
aa3cb20e1e
slice bug corrected
2014-01-20 18:35:52 +01:00
Ahmed Irfan
c347f2825f
assert feature
2014-01-20 10:45:02 +01:00
Ahmed Irfan
9a689f33a5
verilog default options pull
...
shift operator width issues
2014-01-17 19:32:35 +01:00
Ahmed Irfan
c7a2e582aa
slice error corrected
2014-01-16 20:16:01 +01:00
Ahmed Irfan
3a1490888d
width issues
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dff cell for more than one registers
2014-01-15 17:36:33 +01:00
Ahmed Irfan
661b5a993e
BTOR backend
2014-01-14 12:03:53 +01:00
Ahmed Irfan
ffd768ce86
btor
2014-01-03 10:52:44 +01:00