mirror of https://github.com/YosysHQ/yosys.git
Fix indenting and log messages in code merged from opt_compare_pr
This commit is contained in:
Clifford Wolf
parent
19a980277f
commit
ffbe8d41f3
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@ -258,29 +258,30 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative)
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return last_bit_one;
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}
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//if the signal has only one bit set, return the index of that bit.
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//otherwise return -1
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int get_onehot_bit_index(RTLIL::SigSpec signal){
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if(!signal.is_fully_const())
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return -1;
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bool bit_set = false;
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int bit_index = 0;
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int i = 0;
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for(auto bit: signal.bits()){
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if(bit == RTLIL::State::S1){
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if(bit_set)
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return -1;
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bit_index = i;
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bit_set = true;
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}
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i++;
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}
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if(bit_set){
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return bit_index;
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}else{
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return -1;
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}
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// if the signal has only one bit set, return the index of that bit.
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// otherwise return -1
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int get_onehot_bit_index(RTLIL::SigSpec signal)
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{
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int bit_index = -1;
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for (int i = 0; i < GetSize(signal); i++)
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{
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if (signal[i] == RTLIL::State::S0)
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continue;
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if (signal[i] != RTLIL::State::S1)
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return -1;
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if (bit_index != -1)
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return -1;
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bit_index = i;
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}
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return bit_index;
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}
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool clkinv)
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{
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if (!design->selected(module))
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@ -1188,86 +1189,103 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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}
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//replace a <0 or a >=0 with the top bit of a
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if(do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
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{
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bool is_lt = false; //used to decide whether the signal needs to be negated
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RTLIL::SigSpec sigVar; //references the variable signal in the comparison
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RTLIL::SigSpec sigConst; //references the constant signal in the comparison
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//note that this signal must be constant for the optimization
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//to take place, but it is not checked beforehand.
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//If new passes are added, this signal must be checked for const-ness
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int width; //width of the variable port
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bool var_signed;
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if(cell->type == "$lt" || cell->type == "$ge"){
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is_lt = cell->type == "$lt" ? 1 : 0;
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sigVar = cell->getPort("\\A");
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sigConst = cell->getPort("\\B");
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width = cell->parameters["\\A_WIDTH"].as_int();
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var_signed = cell->parameters["\\A_SIGNED"].as_bool();
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}
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if(cell->type == "$gt" || cell->type == "$le"){
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is_lt = cell->type == "$gt" ? 1 : 0;
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sigVar = cell->getPort("\\B");
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sigConst = cell->getPort("\\A");
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width = cell->parameters["\\B_WIDTH"].as_int();
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var_signed = cell->parameters["\\B_SIGNED"].as_bool();
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}
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//replace a(signed) < 0 with the high bit of a
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if(sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true){
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RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
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a_prime[0] = sigVar[width-1];
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if(is_lt){
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log("Optimizing a < 0 with a[%d]\n",width - 1);
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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}
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else{
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log("Optimizing a >= 0 with ~a[%d]\n",width - 1);
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module->addNot(NEW_ID, a_prime, cell->getPort("\\Y"));
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module->remove(cell);
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}
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did_something = true;
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goto next_cell;
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}
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else if(sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false){
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int const_bit_set = get_onehot_bit_index(sigConst);
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if(sigConst.is_fully_zero()){
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RTLIL::SigSpec a_prime(RTLIL::State::S0,1);
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if(is_lt){
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log("replacing a(unsigned) < 0 with constant false\n");
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a_prime[0] = RTLIL::State::S0;
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}
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else{
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log("replacing a(unsigned) >= 0 with constant true\n");
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a_prime[0] = RTLIL::State::S1;
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}
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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else if(const_bit_set >= 0){ //if b has only 1 bit set
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int bit_set = const_bit_set;
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RTLIL::SigSpec a_prime(RTLIL::State::S0,width-bit_set);
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for(int i = bit_set; i < width; i++){
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a_prime[i-bit_set] = sigVar[i];
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}
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if(is_lt){
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log("replacing a < %d with !a[%d:%d]\n",sigConst.as_int(false),width-1,bit_set);
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module->addLogicNot(NEW_ID, a_prime,cell->getPort("\\Y"));
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}
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else{
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log("replacing a >= %d with |a[%d:%d]\n",sigConst.as_int(false),width-1,bit_set);
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module->addReduceOr(NEW_ID, a_prime,cell->getPort("\\Y"));
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}
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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}
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}
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// replace a<0 or a>=0 with the top bit of a
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if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
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{
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//used to decide whether the signal needs to be negated
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bool is_lt = false;
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//references the variable signal in the comparison
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RTLIL::SigSpec sigVar;
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//references the constant signal in the comparison
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RTLIL::SigSpec sigConst;
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// note that this signal must be constant for the optimization
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// to take place, but it is not checked beforehand.
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// If new passes are added, this signal must be checked for const-ness
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//width of the variable port
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int width;
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bool var_signed;
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if (cell->type == "$lt" || cell->type == "$ge") {
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is_lt = cell->type == "$lt" ? 1 : 0;
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sigVar = cell->getPort("\\A");
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sigConst = cell->getPort("\\B");
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width = cell->parameters["\\A_WIDTH"].as_int();
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var_signed = cell->parameters["\\A_SIGNED"].as_bool();
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} else
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if (cell->type == "$gt" || cell->type == "$le") {
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is_lt = cell->type == "$gt" ? 1 : 0;
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sigVar = cell->getPort("\\B");
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sigConst = cell->getPort("\\A");
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width = cell->parameters["\\B_WIDTH"].as_int();
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var_signed = cell->parameters["\\B_SIGNED"].as_bool();
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}
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// replace a(signed) < 0 with the high bit of a
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if (sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true)
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{
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RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
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a_prime[0] = sigVar[width - 1];
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if (is_lt) {
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log("Replacing %s cell `%s' (implementing X<0) with X[%d]: %s\n",
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log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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} else {
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log("Replacing %s cell `%s' (implementing X>=0) with ~X[%d]: %s\n",
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log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
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module->addNot(NEW_ID, a_prime, cell->getPort("\\Y"));
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module->remove(cell);
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}
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did_something = true;
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goto next_cell;
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} else
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if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
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{
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if (sigConst.is_fully_zero()) {
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RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
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if (is_lt) {
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log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
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log_id(cell->type), log_id(cell));
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a_prime[0] = RTLIL::State::S0;
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} else {
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log("Replacing %s cell `%s' (implementing unsigned X>=0) with constant true.\n",
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log_id(cell->type), log_id(cell));
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a_prime[0] = RTLIL::State::S1;
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}
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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int const_bit_set = get_onehot_bit_index(sigConst);
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if (const_bit_set >= 0) {
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int bit_set = const_bit_set;
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RTLIL::SigSpec a_prime(RTLIL::State::S0, width - bit_set);
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for (int i = bit_set; i < width; i++) {
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a_prime[i - bit_set] = sigVar[i];
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}
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if (is_lt) {
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log("Replacing %s cell `%s' (implementing unsigned X<%s) with !X[%d:%d]: %s.\n",
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log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
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module->addLogicNot(NEW_ID, a_prime, cell->getPort("\\Y"));
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} else {
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log("Replacing %s cell `%s' (implementing unsigned X>=%s) with |X[%d:%d]: %s.\n",
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log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
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module->addReduceOr(NEW_ID, a_prime, cell->getPort("\\Y"));
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}
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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}
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}
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next_cell:;
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#undef ACTION_DO
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