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Fix indenting and log messages in code merged from opt_compare_pr

This commit is contained in:
Clifford Wolf 2017-01-31 16:20:56 +01:00
parent 19a980277f
commit ffbe8d41f3
1 changed files with 120 additions and 102 deletions
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92
passes/opt/opt_expr.cc
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@ -258,29 +258,30 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative)
return last_bit_one; return last_bit_one;
} }
// if the signal has only one bit set, return the index of that bit. // if the signal has only one bit set, return the index of that bit.
// otherwise return -1 // otherwise return -1
int get_onehot_bit_index(RTLIL::SigSpec signal){ int get_onehot_bit_index(RTLIL::SigSpec signal)
if(!signal.is_fully_const()) {
int bit_index = -1;
for (int i = 0; i < GetSize(signal); i++)
{
if (signal[i] == RTLIL::State::S0)
continue;
if (signal[i] != RTLIL::State::S1)
return -1; return -1;
bool bit_set = false;
int bit_index = 0; if (bit_index != -1)
int i = 0;
for(auto bit: signal.bits()){
if(bit == RTLIL::State::S1){
if(bit_set)
return -1; return -1;
bit_index = i; bit_index = i;
bit_set = true;
} }
i++;
}
if(bit_set){
return bit_index; return bit_index;
}else{
return -1;
}
} }
void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool clkinv) void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool clkinv)
{ {
if (!design->selected(module)) if (!design->selected(module))
@ -1188,24 +1189,35 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
} }
} }
// replace a<0 or a>=0 with the top bit of a // replace a<0 or a>=0 with the top bit of a
if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le")) if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
{ {
bool is_lt = false; //used to decide whether the signal needs to be negated //used to decide whether the signal needs to be negated
RTLIL::SigSpec sigVar; //references the variable signal in the comparison bool is_lt = false;
RTLIL::SigSpec sigConst; //references the constant signal in the comparison
//references the variable signal in the comparison
RTLIL::SigSpec sigVar;
//references the constant signal in the comparison
RTLIL::SigSpec sigConst;
// note that this signal must be constant for the optimization // note that this signal must be constant for the optimization
// to take place, but it is not checked beforehand. // to take place, but it is not checked beforehand.
// If new passes are added, this signal must be checked for const-ness // If new passes are added, this signal must be checked for const-ness
int width; //width of the variable port
//width of the variable port
int width;
bool var_signed; bool var_signed;
if (cell->type == "$lt" || cell->type == "$ge") { if (cell->type == "$lt" || cell->type == "$ge") {
is_lt = cell->type == "$lt" ? 1 : 0; is_lt = cell->type == "$lt" ? 1 : 0;
sigVar = cell->getPort("\\A"); sigVar = cell->getPort("\\A");
sigConst = cell->getPort("\\B"); sigConst = cell->getPort("\\B");
width = cell->parameters["\\A_WIDTH"].as_int(); width = cell->parameters["\\A_WIDTH"].as_int();
var_signed = cell->parameters["\\A_SIGNED"].as_bool(); var_signed = cell->parameters["\\A_SIGNED"].as_bool();
} } else
if (cell->type == "$gt" || cell->type == "$le") { if (cell->type == "$gt" || cell->type == "$le") {
is_lt = cell->type == "$gt" ? 1 : 0; is_lt = cell->type == "$gt" ? 1 : 0;
sigVar = cell->getPort("\\B"); sigVar = cell->getPort("\\B");
@ -1213,33 +1225,37 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
width = cell->parameters["\\B_WIDTH"].as_int(); width = cell->parameters["\\B_WIDTH"].as_int();
var_signed = cell->parameters["\\B_SIGNED"].as_bool(); var_signed = cell->parameters["\\B_SIGNED"].as_bool();
} }
// replace a(signed) < 0 with the high bit of a // replace a(signed) < 0 with the high bit of a
if(sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true){ if (sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true)
{
RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int()); RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
a_prime[0] = sigVar[width - 1]; a_prime[0] = sigVar[width - 1];
if (is_lt) { if (is_lt) {
log("Optimizing a < 0 with a[%d]\n",width - 1); log("Replacing %s cell `%s' (implementing X<0) with X[%d]: %s\n",
log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
module->connect(cell->getPort("\\Y"), a_prime); module->connect(cell->getPort("\\Y"), a_prime);
module->remove(cell); module->remove(cell);
} } else {
else{ log("Replacing %s cell `%s' (implementing X>=0) with ~X[%d]: %s\n",
log("Optimizing a >= 0 with ~a[%d]\n",width - 1); log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
module->addNot(NEW_ID, a_prime, cell->getPort("\\Y")); module->addNot(NEW_ID, a_prime, cell->getPort("\\Y"));
module->remove(cell); module->remove(cell);
} }
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} } else
else if(sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false){ if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
int const_bit_set = get_onehot_bit_index(sigConst); {
if (sigConst.is_fully_zero()) { if (sigConst.is_fully_zero()) {
RTLIL::SigSpec a_prime(RTLIL::State::S0, 1); RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
if (is_lt) { if (is_lt) {
log("replacing a(unsigned) < 0 with constant false\n"); log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
log_id(cell->type), log_id(cell));
a_prime[0] = RTLIL::State::S0; a_prime[0] = RTLIL::State::S0;
} } else {
else{ log("Replacing %s cell `%s' (implementing unsigned X>=0) with constant true.\n",
log("replacing a(unsigned) >= 0 with constant true\n"); log_id(cell->type), log_id(cell));
a_prime[0] = RTLIL::State::S1; a_prime[0] = RTLIL::State::S1;
} }
module->connect(cell->getPort("\\Y"), a_prime); module->connect(cell->getPort("\\Y"), a_prime);
@ -1248,18 +1264,20 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
goto next_cell; goto next_cell;
} }
else if(const_bit_set >= 0){ //if b has only 1 bit set int const_bit_set = get_onehot_bit_index(sigConst);
if (const_bit_set >= 0) {
int bit_set = const_bit_set; int bit_set = const_bit_set;
RTLIL::SigSpec a_prime(RTLIL::State::S0, width - bit_set); RTLIL::SigSpec a_prime(RTLIL::State::S0, width - bit_set);
for (int i = bit_set; i < width; i++) { for (int i = bit_set; i < width; i++) {
a_prime[i - bit_set] = sigVar[i]; a_prime[i - bit_set] = sigVar[i];
} }
if (is_lt) { if (is_lt) {
log("replacing a < %d with !a[%d:%d]\n",sigConst.as_int(false),width-1,bit_set); log("Replacing %s cell `%s' (implementing unsigned X<%s) with !X[%d:%d]: %s.\n",
log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
module->addLogicNot(NEW_ID, a_prime, cell->getPort("\\Y")); module->addLogicNot(NEW_ID, a_prime, cell->getPort("\\Y"));
} } else {
else{ log("Replacing %s cell `%s' (implementing unsigned X>=%s) with |X[%d:%d]: %s.\n",
log("replacing a >= %d with |a[%d:%d]\n",sigConst.as_int(false),width-1,bit_set); log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
module->addReduceOr(NEW_ID, a_prime, cell->getPort("\\Y")); module->addReduceOr(NEW_ID, a_prime, cell->getPort("\\Y"));
} }
module->remove(cell); module->remove(cell);