mirror of https://github.com/YosysHQ/yosys.git
xaiger: output $_DFF_[NP]_ with mergeability if -dff option
This commit is contained in:
Eddie Hung
parent
5bcde7ccc3
commit
ffa52738fb
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@ -137,7 +137,7 @@ struct XAigerWriter
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return a;
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}
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XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
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XAigerWriter(Module *module, bool dff_mode, bool holes_mode=false) : module(module), sigmap(module)
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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@ -212,10 +212,7 @@ struct XAigerWriter
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continue;
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}
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if (cell->type == ID($__ABC9_FF_) &&
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// The presence of an abc9_mergeability attribute indicates
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// that we do want to pass this flop to ABC
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cell->attributes.count(ID::abc9_mergeability))
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if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
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{
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SigBit D = sigmap(cell->getPort(ID::D).as_bit());
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SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
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@ -233,7 +230,11 @@ struct XAigerWriter
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module) {
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IdString derived_type = inst_module->derive(module->design, cell->parameters);
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IdString derived_type;
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if (cell->parameters.empty())
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derived_type = cell->type;
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else
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derived_type = inst_module->derive(module->design, cell->parameters);
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inst_module = module->design->module(derived_type);
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log_assert(inst_module);
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@ -319,7 +320,7 @@ struct XAigerWriter
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RTLIL::Module* box_module = module->design->module(cell->type);
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log_assert(box_module);
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log_assert(box_module->attributes.count(ID::abc9_box_id) || box_module->get_bool_attribute(ID::abc9_flop));
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log_assert(box_module->attributes.count(ID::abc9_box_id));
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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@ -383,27 +384,6 @@ struct XAigerWriter
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undriven_bits.erase(O);
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}
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}
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// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
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if (box_module->get_bool_attribute(ID::abc9_flop)) {
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SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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if (rhs.empty())
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log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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b = State::S0;
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else if (I != b) {
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if (I == RTLIL::Sx)
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alias_map[b] = State::S0;
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else
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alias_map[b] = I;
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}
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co_bits.emplace_back(b);
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unused_bits.erase(I);
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}
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}
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}
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for (auto bit : input_bits)
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@ -593,7 +573,11 @@ struct XAigerWriter
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RTLIL::Module* box_module = module->design->module(cell->type);
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log_assert(box_module);
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IdString derived_type = box_module->derive(box_module->design, cell->parameters);
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IdString derived_type;
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if (cell->parameters.empty())
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derived_type = cell->type;
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else
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derived_type = box_module->derive(module->design, cell->parameters);
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box_module = box_module->design->module(derived_type);
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log_assert(box_module);
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@ -610,11 +594,6 @@ struct XAigerWriter
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box_outputs += GetSize(w);
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}
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// For flops only, create an extra 1-bit input that drives a new wire
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// called "<cell>.abc9_ff.Q" that is used below
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if (box_module->get_bool_attribute(ID::abc9_flop))
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box_inputs++;
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std::get<0>(v) = box_inputs;
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std::get<1>(v) = box_outputs;
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std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
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@ -635,18 +614,34 @@ struct XAigerWriter
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auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
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write_s_buffer(ff_bits.size());
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dict<SigBit, int> clk_to_mergeability;
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bool nonzero_warned = false;
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for (const auto &i : ff_bits) {
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const SigBit &d = i.first;
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const Cell *cell = i.second;
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int mergeability = cell->attributes.at(ID::abc9_mergeability).as_int();
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log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_)));
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SigBit clock = sigmap(cell->getPort(ID::C));
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auto r = clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size() + 1));
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int mergeability = r.first->second;
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log_assert(mergeability > 0);
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if (cell->type == ID($_DFF_N_))
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write_r_buffer(-mergeability);
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else if (cell->type == ID($_DFF_P_))
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write_r_buffer(mergeability);
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else log_abort();
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Const init = cell->attributes.at(ID::abc9_init, State::Sx);
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log_assert(GetSize(init) == 1);
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if (init == State::S1)
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if (init == State::S1) {
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if (!nonzero_warned) {
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log_warning("Module '%s' contains $_DFF_[NP]_ cell with non-zero initial state -- unsupported by ABC9.\n", log_id(module));
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nonzero_warned = true;
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}
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write_s_buffer(1);
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}
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else if (init == State::S0)
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write_s_buffer(0);
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else {
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@ -674,7 +669,7 @@ struct XAigerWriter
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RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
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if (holes_module) {
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, true /* holes_mode */);
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XAigerWriter writer(holes_module, false /* dff_mode */, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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f << "a";
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@ -761,8 +756,8 @@ struct XAigerBackend : public Backend {
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log(" write_xaiger [options] [filename]\n");
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log("\n");
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log("Write the top module (according to the (* top *) attribute or if only one module\n");
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log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
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log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
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log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_DFF_N_,\n");
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log(" $_DFF_P_, or non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
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log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
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log("module, if it exists.\n");
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log("\n");
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@ -772,10 +767,13 @@ struct XAigerBackend : public Backend {
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log(" -map <filename>\n");
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log(" write an extra file with port and box symbols\n");
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log("\n");
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log(" -dff\n");
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log(" write $_DFF_[NP]_ cells\n");
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log("\n");
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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bool ascii_mode = false;
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bool ascii_mode = false, dff_mode = false;
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std::string map_filename;
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log_header(design, "Executing XAIGER backend.\n");
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@ -791,6 +789,10 @@ struct XAigerBackend : public Backend {
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map_filename = args[++argidx];
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continue;
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}
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if (args[argidx] == "-dff") {
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dff_mode = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx, !ascii_mode);
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@ -808,7 +810,7 @@ struct XAigerBackend : public Backend {
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if (!top_module->memories.empty())
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log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
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XAigerWriter writer(top_module);
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XAigerWriter writer(top_module, dff_mode);
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writer.write_aiger(*f, ascii_mode);
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if (!map_filename.empty()) {
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