mirror of https://github.com/YosysHQ/yosys.git
wreduce: Group reconnections
Group the reconnections, so that instead of producing connect $auto$wreduce.cc:455:run$24 [0] 1'0 connect $auto$wreduce.cc:455:run$23 [31] 1'0 connect $auto$wreduce.cc:455:run$23 [30] 1'0 ... (40 more lines) we produce connect $auto$wreduce.cc:461:run$23 [31:11] 21'000000000000000000000 connect $auto$wreduce.cc:461:run$24 [31:10] 22'0000000000000000000000 .
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@ -364,10 +364,16 @@ struct WreduceWorker
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if (cell->type == ID($mul))
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max_y_size = a_size + b_size;
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while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) {
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module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : State::S0);
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sig.remove(GetSize(sig)-1);
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bits_removed++;
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max_y_size = std::max(max_y_size, 1);
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if (GetSize(sig) > max_y_size) {
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SigSpec extra_bits = sig.extract(max_y_size, GetSize(sig) - max_y_size);
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bits_removed += GetSize(extra_bits);
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sig.remove(max_y_size, GetSize(extra_bits));
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SigBit padbit = is_signed ? sig[GetSize(sig)-1] : State::S0;
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module->connect(extra_bits, SigSpec(padbit, GetSize(extra_bits)));
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}
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}
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