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Proper SigBit forming in sim

This commit is contained in:
Miodrag Milanovic 2022-03-22 14:22:32 +01:00
parent f45b290820
commit ff3b0c2c46
1 changed files with 4 additions and 4 deletions
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8
passes/sat/sim.cc
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@ -1138,13 +1138,13 @@ struct SimWorker : SimShared
if (index < w->start_offset || index > w->start_offset + w->width) if (index < w->start_offset || index > w->start_offset + w->width)
log_error("Index %d for wire %s is out of range\n", index, log_signal(w)); log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
if (type == "input") { if (type == "input") {
inputs[variable] = {SigBit(w,index), false}; inputs[variable] = {SigBit(w,index-w->start_offset), false};
} else if (type == "init") { } else if (type == "init") {
inits[variable] = {SigBit(w,index), false}; inits[variable] = {SigBit(w,index-w->start_offset), false};
} else if (type == "latch") { } else if (type == "latch") {
latches[variable] = {SigBit(w,index), false}; latches[variable] = {SigBit(w,index-w->start_offset), false};
} else if (type == "invlatch") { } else if (type == "invlatch") {
latches[variable] = {SigBit(w,index), true}; latches[variable] = {SigBit(w,index-w->start_offset), true};
} }
} }