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synth_xilinx to techmap FFs after abc call, otherwise -retime fails

This commit is contained in:
Eddie Hung 2019-04-05 14:43:06 -07:00
parent 19271bd996
commit ff0912c75e
1 changed files with 3 additions and 3 deletions
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6
techlibs/xilinx/synth_xilinx.cc
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@ -256,9 +256,9 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "opt -full"); Pass::call(design, "opt -full");
if (vpr) { if (vpr) {
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
} else { } else {
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
} }
Pass::call(design, "hierarchy -check"); Pass::call(design, "hierarchy -check");
@ -269,7 +269,7 @@ struct SynthXilinxPass : public Pass
{ {
Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, "clean"); Pass::call(design, "clean");
Pass::call(design, "techmap -map +/xilinx/lut_map.v"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
} }
if (check_label(active, run_from, run_to, "map_cells")) if (check_label(active, run_from, run_to, "map_cells"))