mirror of https://github.com/YosysHQ/yosys.git
synth_xilinx to call bitblast_shiftx
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@ -126,6 +126,7 @@ struct SynthXilinxPass : public Pass
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log("\n");
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log("\n");
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log(" map_cells:\n");
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log(" map_cells:\n");
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log(" pmux2shiftx (without '-nosrl' and '-nomux' only)\n");
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log(" pmux2shiftx (without '-nosrl' and '-nomux' only)\n");
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log(" bitblast_shiftx (without '-nosrl' and '-nomux' only)\n");
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log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
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log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
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log(" opt_expr -mux_undef (without '-nosrl' only)\n");
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log(" opt_expr -mux_undef (without '-nosrl' only)\n");
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log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
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log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
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@ -309,8 +310,10 @@ struct SynthXilinxPass : public Pass
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// cells for identifying variable-length shift registers,
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// cells for identifying variable-length shift registers,
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// so attempt to convert $pmux-es to the former
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// so attempt to convert $pmux-es to the former
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// Also: wide multiplexer inference benefits from this too
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// Also: wide multiplexer inference benefits from this too
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if (!nosrl || !nomux)
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if (!nosrl || !nomux) {
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Pass::call(design, "pmux2shiftx");
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Pass::call(design, "pmux2shiftx");
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Pass::call(design, "bitblast_shiftx");
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}
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if (!nosrl) {
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if (!nosrl) {
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// shregmap operates on bit-level flops, not word-level,
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// shregmap operates on bit-level flops, not word-level,
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