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Fixed Verific parser error in ice40 cell library 

non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
This commit is contained in:
Claire Xenia Wolf 2021-10-19 12:33:01 +02:00
parent affed103e0
commit fe9689c136
1 changed files with 62 additions and 22 deletions
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84
techlibs/ice40/cells_sim.v
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@ -1,6 +1,6 @@
`timescale 1ps / 1ps
`define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q
`define SB_DFF_INIT initial Q = 0;
// `define SB_DFF_INIT
`ifndef NO_ICE40_DEFAULT_ASSIGNMENTS
`define ICE40_DEFAULT_ASSIGNMENT_V(v) = v
@ -263,9 +263,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFF (
output `SB_DFF_REG,
output reg Q,
input C, D
);
`SB_DFF_INIT
always @(posedge C)
Q <= D;
`ifdef ICE40_HX
@ -299,9 +301,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFE (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D
);
`SB_DFF_INIT
always @(posedge C)
if (E)
Q <= D;
@ -342,9 +346,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFSR (
output `SB_DFF_REG,
output reg Q,
input C, R, D
);
`SB_DFF_INIT
always @(posedge C)
if (R)
Q <= 0;
@ -390,9 +396,11 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFR (
output `SB_DFF_REG,
output reg Q,
input C, R, D
);
`SB_DFF_INIT
always @(posedge C, posedge R)
if (R)
Q <= 0;
@ -459,9 +467,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFSS (
output `SB_DFF_REG,
output reg Q,
input C, S, D
);
`SB_DFF_INIT
always @(posedge C)
if (S)
Q <= 1;
@ -507,9 +517,11 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFS (
output `SB_DFF_REG,
output reg Q,
input C, S, D
);
`SB_DFF_INIT
always @(posedge C, posedge S)
if (S)
Q <= 1;
@ -576,9 +588,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFESR (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
`SB_DFF_INIT
always @(posedge C)
if (E) begin
if (R)
@ -632,9 +646,11 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFER (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
`SB_DFF_INIT
always @(posedge C, posedge R)
if (R)
Q <= 0;
@ -707,9 +723,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFESS (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
`SB_DFF_INIT
always @(posedge C)
if (E) begin
if (S)
@ -763,9 +781,11 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFES (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
`SB_DFF_INIT
always @(posedge C, posedge S)
if (S)
Q <= 1;
@ -840,9 +860,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFN (
output `SB_DFF_REG,
output reg Q,
input C, D
);
`SB_DFF_INIT
always @(negedge C)
Q <= D;
`ifdef ICE40_HX
@ -876,9 +898,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNE (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D
);
`SB_DFF_INIT
always @(negedge C)
if (E)
Q <= D;
@ -919,9 +943,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNSR (
output `SB_DFF_REG,
output reg Q,
input C, R, D
);
`SB_DFF_INIT
always @(negedge C)
if (R)
Q <= 0;
@ -967,9 +993,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNR (
output `SB_DFF_REG,
output reg Q,
input C, R, D
);
`SB_DFF_INIT
always @(negedge C, posedge R)
if (R)
Q <= 0;
@ -1036,9 +1064,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNSS (
output `SB_DFF_REG,
output reg Q,
input C, S, D
);
`SB_DFF_INIT
always @(negedge C)
if (S)
Q <= 1;
@ -1084,9 +1114,11 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFNS (
output `SB_DFF_REG,
output reg Q,
input C, S, D
);
`SB_DFF_INIT
always @(negedge C, posedge S)
if (S)
Q <= 1;
@ -1153,9 +1185,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNESR (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
`SB_DFF_INIT
always @(negedge C)
if (E) begin
if (R)
@ -1209,9 +1243,11 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFNER (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
`SB_DFF_INIT
always @(negedge C, posedge R)
if (R)
Q <= 0;
@ -1284,9 +1320,11 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNESS (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
`SB_DFF_INIT
always @(negedge C)
if (E) begin
if (S)
@ -1340,9 +1378,11 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFNES (
output `SB_DFF_REG,
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
`SB_DFF_INIT
always @(negedge C, posedge S)
if (S)
Q <= 1;