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Added log_warning() API

This commit is contained in:
Clifford Wolf 2014-11-09 10:44:23 +01:00
parent cb9e10b462
commit fe829bdbdc
15 changed files with 57 additions and 34 deletions
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2
backends/spice/spice.cc
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@ -58,7 +58,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
if (design->modules_.count(cell->type) == 0) if (design->modules_.count(cell->type) == 0)
{ {
log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name)); RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
RTLIL::SigSpec sig = sigmap(conn.second); RTLIL::SigSpec sig = sigmap(conn.second);

12
frontends/ast/genrtlil.cc
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@ -869,7 +869,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_REALVALUE: case AST_REALVALUE:
{ {
RTLIL::SigSpec sig = realAsConst(width_hint); RTLIL::SigSpec sig = realAsConst(width_hint);
log("Warning: converting real value %e to binary %s at %s:%d.\n", log_warning("converting real value %e to binary %s at %s:%d.\n",
realvalue, log_signal(sig), filename.c_str(), linenum); realvalue, log_signal(sig), filename.c_str(), linenum);
return sig; return sig;
} }
@ -890,7 +890,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
wire->name = str; wire->name = str;
if (flag_autowire) if (flag_autowire)
log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
else else
log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum); log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum);
} }
@ -955,10 +955,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width); chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) { if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
if (chunk.width == 1) if (chunk.width == 1)
log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n", log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
str.c_str(), filename.c_str(), linenum); str.c_str(), filename.c_str(), linenum);
else else
log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n", log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
str.c_str(), filename.c_str(), linenum, chunk.width); str.c_str(), filename.c_str(), linenum, chunk.width);
chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
} else { } else {
@ -972,10 +972,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset += add_undef_bits_lsb; chunk.offset += add_undef_bits_lsb;
} }
if (add_undef_bits_lsb) if (add_undef_bits_lsb)
log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n", log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb); str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb);
if (add_undef_bits_msb) if (add_undef_bits_msb)
log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n", log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
str.c_str(), filename.c_str(), linenum, add_undef_bits_msb); str.c_str(), filename.c_str(), linenum, add_undef_bits_msb);
} }
} }

8
frontends/ast/simplify.cc
View File

@ -102,7 +102,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
verbose_activate: verbose_activate:
if (mem2reg_set.count(mem) == 0) { if (mem2reg_set.count(mem) == 0) {
log("Warning: Replacing memory %s with list of registers.", mem->str.c_str()); log_warning("Replacing memory %s with list of registers.", mem->str.c_str());
bool first_element = true; bool first_element = true;
for (auto &place : mem2reg_places[it.first]) { for (auto &place : mem2reg_places[it.first]) {
log("%s%s", first_element ? " See " : ", ", place.c_str()); log("%s%s", first_element ? " See " : ", ", place.c_str());
@ -648,7 +648,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
int width = children[1]->range_left - children[1]->range_right + 1; int width = children[1]->range_left - children[1]->range_right + 1;
if (children[0]->type == AST_REALVALUE) { if (children[0]->type == AST_REALVALUE) {
RTLIL::Const constvalue = children[0]->realAsConst(width); RTLIL::Const constvalue = children[0]->realAsConst(width);
log("Warning: converting real value %e to binary %s at %s:%d.\n", log_warning("converting real value %e to binary %s at %s:%d.\n",
children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum); children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum);
delete children[0]; delete children[0];
children[0] = mkconst_bits(constvalue.bits, sign_hint); children[0] = mkconst_bits(constvalue.bits, sign_hint);
@ -690,7 +690,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
} }
} }
if (current_scope.count(str) == 0) { if (current_scope.count(str) == 0) {
// log("Warning: Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str()); // log_warning("Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str());
AstNode *auto_wire = new AstNode(AST_AUTOWIRE); AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
auto_wire->str = str; auto_wire->str = str;
current_ast_mod->children.push_back(auto_wire); current_ast_mod->children.push_back(auto_wire);
@ -1260,7 +1260,7 @@ skip_dynamic_range_lvalue_expansion:;
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN"; std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
if (type == AST_ASSIGN_EQ) if (type == AST_ASSIGN_EQ)
log("Warning: Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n", log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n",
filename.c_str(), linenum); filename.c_str(), linenum);
int mem_width, mem_size, addr_bits; int mem_width, mem_size, addr_bits;

2
frontends/verific/verific.cc
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@ -730,7 +730,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
if (import_netlist_instance_cells(module, net_map, inst)) if (import_netlist_instance_cells(module, net_map, inst))
continue; continue;
if (inst->IsOperator()) if (inst->IsOperator())
log("Warning: Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name()); log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name());
} else { } else {
if (import_netlist_instance_gates(module, net_map, inst)) if (import_netlist_instance_gates(module, net_map, inst))
continue; continue;

12
frontends/verilog/verilog_lexer.l
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@ -254,8 +254,8 @@ supply1 { return TOK_SUPPLY1; }
} }
"/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" { "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
log("Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"); log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
log("It is strongly suggested to use `ifdef constructs instead!\n"); "It is strongly suggested to use `ifdef constructs instead!\n");
BEGIN(SYNOPSYS_TRANSLATE_OFF); BEGIN(SYNOPSYS_TRANSLATE_OFF);
} }
<SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */ <SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */
@ -266,13 +266,13 @@ supply1 { return TOK_SUPPLY1; }
BEGIN(SYNOPSYS_FLAGS); BEGIN(SYNOPSYS_FLAGS);
} }
<SYNOPSYS_FLAGS>full_case { <SYNOPSYS_FLAGS>full_case {
log("Warning: Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"); log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
log("It is strongly suggested to use verilog x-values and default branches instead!\n"); "It is strongly suggested to use verilog x-values and default branches instead!\n");
return TOK_SYNOPSYS_FULL_CASE; return TOK_SYNOPSYS_FULL_CASE;
} }
<SYNOPSYS_FLAGS>parallel_case { <SYNOPSYS_FLAGS>parallel_case {
log("Warning: Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"); log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n"); "It is strongly suggested to use verilog `parallel_case' attributes instead!\n");
return TOK_SYNOPSYS_PARALLEL_CASE; return TOK_SYNOPSYS_PARALLEL_CASE;
} }
<SYNOPSYS_FLAGS>. /* ignore everything else */ <SYNOPSYS_FLAGS>. /* ignore everything else */

2
kernel/cost.h
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@ -70,7 +70,7 @@ int get_cell_cost(RTLIL::IdString type, const std::map<RTLIL::IdString, RTLIL::C
return module_cost; return module_cost;
} }
log("Warning: Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters)); log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
return 1; return 1;
} }

25
kernel/log.cc
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@ -152,6 +152,19 @@ void logv_header(const char *format, va_list ap)
log_files.pop_back(); log_files.pop_back();
} }
void logv_warning(const char *format, va_list ap)
{
if (log_errfile != NULL)
log_files.push_back(log_errfile);
log("Warning: ");
logv(format, ap);
log_flush();
if (log_errfile != NULL)
log_files.pop_back();
}
void logv_error(const char *format, va_list ap) void logv_error(const char *format, va_list ap)
{ {
if (log_errfile != NULL) if (log_errfile != NULL)
@ -179,6 +192,14 @@ void log_header(const char *format, ...)
va_end(ap); va_end(ap);
} }
void log_warning(const char *format, ...)
{
va_list ap;
va_start(ap, format);
logv_warning(format, ap);
va_end(ap);
}
void log_error(const char *format, ...) void log_error(const char *format, ...)
{ {
va_list ap; va_list ap;
@ -304,14 +325,14 @@ std::map<std::string, std::pair<std::string, int>> get_coverage_data()
for (auto &it : extra_coverage_data) { for (auto &it : extra_coverage_data) {
if (coverage_data.count(it.first)) if (coverage_data.count(it.first))
log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str()); log_warning("found duplicate coverage id \"%s\".\n", it.first.c_str());
coverage_data[it.first].first = it.second.first; coverage_data[it.first].first = it.second.first;
coverage_data[it.first].second += it.second.second; coverage_data[it.first].second += it.second.second;
} }
for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) { for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) {
if (coverage_data.count(p->id)) if (coverage_data.count(p->id))
log("WARNING: found duplicate coverage id \"%s\".\n", p->id); log_warning("found duplicate coverage id \"%s\".\n", p->id);
coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func); coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
coverage_data[p->id].second += p->counter; coverage_data[p->id].second += p->counter;
} }

4
kernel/log.h
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@ -51,10 +51,12 @@ extern int log_verbose_level;
void logv(const char *format, va_list ap); void logv(const char *format, va_list ap);
void logv_header(const char *format, va_list ap); void logv_header(const char *format, va_list ap);
void logv_warning(const char *format, va_list ap);
_NORETURN_ void logv_error(const char *format, va_list ap) __attribute__((noreturn));
void logv_error(const char *format, va_list ap) __attribute__((noreturn));
void log(const char *format, ...) __attribute__((format(printf, 1, 2))); void log(const char *format, ...) __attribute__((format(printf, 1, 2)));
void log_header(const char *format, ...) __attribute__((format(printf, 1, 2))); void log_header(const char *format, ...) __attribute__((format(printf, 1, 2)));
void log_warning(const char *format, ...) __attribute__((format(printf, 1, 2)));
_NORETURN_ void log_error(const char *format, ...) __attribute__((format(printf, 1, 2))) __attribute__((noreturn)); _NORETURN_ void log_error(const char *format, ...) __attribute__((format(printf, 1, 2))) __attribute__((noreturn));
_NORETURN_ void log_cmd_error(const char *format, ...) __attribute__((format(printf, 1, 2))) __attribute__((noreturn)); _NORETURN_ void log_cmd_error(const char *format, ...) __attribute__((format(printf, 1, 2))) __attribute__((noreturn));

6
kernel/rtlil.cc
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@ -440,7 +440,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
if (selected_whole_module(it.first)) if (selected_whole_module(it.first))
result.push_back(it.second); result.push_back(it.second);
else if (selected_module(it.first)) else if (selected_module(it.first))
log("Warning: Ignoring partially selected module %s.\n", log_id(it.first)); log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
return result; return result;
} }
@ -1062,14 +1062,14 @@ bool RTLIL::Module::has_processes() const
bool RTLIL::Module::has_memories_warn() const bool RTLIL::Module::has_memories_warn() const
{ {
if (!memories.empty()) if (!memories.empty())
log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this)); log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
return !memories.empty(); return !memories.empty();
} }
bool RTLIL::Module::has_processes_warn() const bool RTLIL::Module::has_processes_warn() const
{ {
if (!processes.empty()) if (!processes.empty())
log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this)); log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
return !processes.empty(); return !processes.empty();
} }

2
passes/cmds/select.cc
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@ -532,7 +532,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode)
} }
if (rem_objects == 0) if (rem_objects == 0)
log("Warning: reached configured limit at `%s'.\n", arg.c_str()); log_warning("reached configured limit at `%s'.\n", arg.c_str());
} }
static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel) static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)

2
passes/fsm/fsm_detect.cc
View File

@ -43,7 +43,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
return true; return true;
if (recursion_monitor.check_any(sig)) { if (recursion_monitor.check_any(sig)) {
log("Warning: logic loop in mux tree at signal %s in module %s.\n", log_warning("logic loop in mux tree at signal %s in module %s.\n",
log_signal(sig), RTLIL::id2cstr(module->name)); log_signal(sig), RTLIL::id2cstr(module->name));
return false; return false;
} }

4
passes/hierarchy/submod.cc
View File

@ -85,7 +85,7 @@ struct SubmodWorker
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false); flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
} else { } else {
log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
flag_signal(conn.second, true, true, true, false, false); flag_signal(conn.second, true, true, true, false, false);
} }
@ -102,7 +102,7 @@ struct SubmodWorker
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
flag_signal(conn.second, false, false, false, true, true); flag_signal(conn.second, false, false, false, true, true);
if (flag_found_something) if (flag_found_something)
log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
} }
} }

4
passes/proc/proc_dff.cc
View File

@ -333,12 +333,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
if (many_async_rules.size() > 0) if (many_async_rules.size() > 0)
{ {
log("WARNING: Complex async reset for dff `%s'.\n", log_signal(sig)); log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc); gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc);
} }
else if (!rstval.is_fully_const() && !ce.eval(rstval)) else if (!rstval.is_fully_const() && !ce.eval(rstval))
{ {
log("WARNING: Async reset value `%s' is not constant!\n", log_signal(rstval)); log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
gen_dffsr(mod, insig, rstval, sig, gen_dffsr(mod, insig, rstval, sig,
sync_edge->type == RTLIL::SyncType::STp, sync_edge->type == RTLIL::SyncType::STp,
sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_level && sync_level->type == RTLIL::SyncType::ST1,

2
passes/sat/eval.cc
View File

@ -277,7 +277,7 @@ struct VlogHammerReporter
while (!ce.eval(sig, undef)) { while (!ce.eval(sig, undef)) {
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef)); // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name)); log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
} }

4
passes/sat/sat.cc
View File

@ -116,7 +116,7 @@ struct SatHelper
} }
if (removed_bits.size()) if (removed_bits.size())
log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); log_warning("ignoring initial value on non-register: %s\n", log_signal(removed_bits));
if (lhs.size()) { if (lhs.size()) {
log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
@ -327,7 +327,7 @@ struct SatHelper
show_drivers.insert(sigmap(p.second), c.second); show_drivers.insert(sigmap(p.second), c.second);
import_cell_counter++; import_cell_counter++;
} else if (ignore_unknown_cells) } else if (ignore_unknown_cells)
log("Warning: Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); log_warning("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
else else
log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
} }