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ice40: add synth_ice40 -dff option, support with -abc9

This commit is contained in:
Eddie Hung 2020-04-13 17:32:21 -07:00
parent 4a10c87ae1
commit fe7965e0ee
2 changed files with 41 additions and 8 deletions
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13
techlibs/ice40/cells_sim.v
View File

@ -245,6 +245,7 @@ endmodule
// Positive Edge SiliconBlue FF Cells // Positive Edge SiliconBlue FF Cells
(* abc9_flop, lib_whitebox *)
module SB_DFF ( module SB_DFF (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, D input C, D
@ -280,6 +281,7 @@ module SB_DFF (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFE ( module SB_DFFE (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, D input C, E, D
@ -322,6 +324,7 @@ module SB_DFFE (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFSR ( module SB_DFFSR (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, R, D input C, R, D
@ -419,6 +422,7 @@ module SB_DFFR (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFSS ( module SB_DFFSS (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, S, D input C, S, D
@ -516,6 +520,7 @@ module SB_DFFS (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFESR ( module SB_DFFESR (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, R, D input C, E, R, D
@ -627,6 +632,7 @@ module SB_DFFER (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFESS ( module SB_DFFESS (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, S, D input C, E, S, D
@ -740,6 +746,7 @@ endmodule
// Negative Edge SiliconBlue FF Cells // Negative Edge SiliconBlue FF Cells
(* abc9_flop, lib_whitebox *)
module SB_DFFN ( module SB_DFFN (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, D input C, D
@ -775,6 +782,7 @@ module SB_DFFN (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNE ( module SB_DFFNE (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, D input C, E, D
@ -817,6 +825,7 @@ module SB_DFFNE (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNSR ( module SB_DFFNSR (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, R, D input C, R, D
@ -864,6 +873,7 @@ module SB_DFFNSR (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNR ( module SB_DFFNR (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, R, D input C, R, D
@ -914,6 +924,7 @@ module SB_DFFNR (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNSS ( module SB_DFFNSS (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, S, D input C, S, D
@ -1011,6 +1022,7 @@ module SB_DFFNS (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNESR ( module SB_DFFNESR (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, R, D input C, E, R, D
@ -1122,6 +1134,7 @@ module SB_DFFNER (
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNESS ( module SB_DFFNESS (
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, S, D input C, E, S, D

36
techlibs/ice40/synth_ice40.cc
View File

@ -71,6 +71,9 @@ struct SynthIce40Pass : public ScriptPass
log(" -noflatten\n"); log(" -noflatten\n");
log(" do not flatten design before synthesis\n"); log(" do not flatten design before synthesis\n");
log("\n"); log("\n");
log(" -dff\n");
log(" run 'abc'/'abc9' with -dff option\n");
log("\n");
log(" -retime\n"); log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n"); log(" run 'abc' with '-dff -D 1' options\n");
log("\n"); log("\n");
@ -113,7 +116,7 @@ struct SynthIce40Pass : public ScriptPass
} }
string top_opt, blif_file, edif_file, json_file, device_opt; string top_opt, blif_file, edif_file, json_file, device_opt;
bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, flowmap; bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap;
int min_ce_use; int min_ce_use;
void clear_flags() YS_OVERRIDE void clear_flags() YS_OVERRIDE
@ -221,6 +224,10 @@ struct SynthIce40Pass : public ScriptPass
abc9 = true; abc9 = true;
continue; continue;
} }
if (args[argidx] == "-dff") {
dff = true;
continue;
}
if (args[argidx] == "-device" && argidx+1 < args.size()) { if (args[argidx] == "-device" && argidx+1 < args.size()) {
device_opt = args[++argidx]; device_opt = args[++argidx];
continue; continue;
@ -354,7 +361,9 @@ struct SynthIce40Pass : public ScriptPass
run(stringf("dff2dffe -unmap-mince %d", min_ce_use)); run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
run("simplemap t:$dff"); run("simplemap t:$dff");
} }
run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v"); if ((abc9 && dff) || help_mode)
run("zinit -all", "(-abc9 and -dff only)");
run("techmap -map +/ice40/ff_map.v");
run("opt_expr -mux_undef"); run("opt_expr -mux_undef");
run("simplemap"); run("simplemap");
run("ice40_ffinit"); run("ice40_ffinit");
@ -387,23 +396,34 @@ struct SynthIce40Pass : public ScriptPass
k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str()); k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
} }
if (dff)
abc9_opts += " -dff";
run("abc9 " + abc9_opts); run("abc9 " + abc9_opts);
} }
else else
run("abc -dress -lut 4", "(skip if -noabc)"); run(stringf("abc -dress -lut 4 %s", dff ? "-dff" : ""), "(skip if -noabc)");
} }
run("ice40_wrapcarry -unwrap"); run("ice40_wrapcarry -unwrap");
run("techmap -D NO_LUT -map +/ice40/cells_map.v"); run("techmap -map +/ice40/ff_map.v");
run("clean"); run("clean");
run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0"); run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
} }
if (check_label("map_cells")) if (check_label("map_cells"))
{ {
if (vpr) if (help_mode)
run("techmap -D NO_LUT -map +/ice40/cells_map.v"); run("techmap [-map +/ice40/ff_map.v] [-map +/ice40/cells_map.v]", "(skip if -abc9; skip if -vpr)");
else else if (vpr)
run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)"); run("techmap -map +/ice40/ff_map.v");
else {
std::string techmap_args;
if (!abc9)
techmap_args += " -map +/ice40/ff_map.v";
if (!vpr)
techmap_args += " -map +/ice40/cells_map.v";
if (!techmap_args.empty())
run("techmap " + techmap_args);
}
run("clean"); run("clean");
} }