mirror of https://github.com/YosysHQ/yosys.git
abstract: factor out emit_mux_anyseq
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27928f74ac
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fe4642887a
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@ -11,9 +11,24 @@ struct EnableLogic {
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bool pol;
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};
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void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_output, EnableLogic enable) {
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auto anyseq = mod->Anyseq(NEW_ID, mux_input.size());
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SigSpec mux_a, mux_b;
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if (enable.pol) {
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mux_a = mux_input;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = mux_input;
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}
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable.wire,
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mux_output);
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}
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bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, EnableLogic enable) {
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// Construct abstract value
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auto anyseq = ff.module->Anyseq(NEW_ID, offsets.size());
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Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size());
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SigSpec mux_input;
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int abstracted_idx = 0;
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@ -27,19 +42,7 @@ bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, E
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abstracted_idx++;
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}
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}
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SigSpec mux_a, mux_b;
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if (enable.pol) {
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mux_a = mux_input;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = mux_input;
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}
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(void)ff.module->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable.wire,
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abstracted);
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emit_mux_anyseq(ff.module, mux_input, abstracted, enable);
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(void)ff.emit();
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return true;
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}
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@ -102,7 +105,6 @@ unsigned int abstract_state(Module* mod, EnableLogic enable) {
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}
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bool abstract_value_port(Module* mod, Cell* cell, std::set<int> offsets, IdString port_name, EnableLogic enable) {
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auto anyseq = mod->Anyseq(NEW_ID, offsets.size());
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Wire* to_abstract = mod->addWire(NEW_ID, offsets.size());
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SigSpec mux_input;
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SigSpec mux_output;
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@ -121,19 +123,7 @@ bool abstract_value_port(Module* mod, Cell* cell, std::set<int> offsets, IdStrin
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}
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}
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cell->setPort(port_name, new_port);
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SigSpec mux_a, mux_b;
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if (enable.pol) {
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mux_a = mux_input;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = mux_input;
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}
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable.wire,
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mux_output);
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emit_mux_anyseq(mod, mux_input, mux_output, enable);
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return true;
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}
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