riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' into btor-ng

This commit is contained in:
Clifford Wolf 2017-12-09 05:26:02 +01:00
parent 68c6675130 50da3bdbcc
commit fd83e3442d
4 changed files with 9 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Makefile
View File

@ -101,7 +101,7 @@ OBJS = kernel/version_$(GIT_REV).o
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
ABCREV = f6838749f234
ABCREV = 31fc97b0aeed
ABCPULL = 1
ABCURL ?= https://bitbucket.org/alanmi/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
@ -439,8 +439,8 @@ ifneq ($(ABCREV),default)
$(Q) if test "`cd abc 2> /dev/null && hg identify | cut -f1 -d' '`" != "$(ABCREV)"; then \
test $(ABCPULL) -ne 0 || { echo 'REEBE: NOP abg hc gb qngr naq NOPCHYY frg gb 0 va Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; exit 1; }; \
echo "Pulling ABC from $(ABCURL):"; set -x; \
test -d abc || hg clone $(ABCURL) abc; \
cd abc && $(MAKE) DEP= clean && hg pull && hg update -r $(ABCREV); \
test -d abc || hg clone --insecure $(ABCURL) abc; \
cd abc && $(MAKE) DEP= clean && hg pull --insecure && hg update -r $(ABCREV); \
fi
endif
$(Q) rm -f abc/abc-[0-9a-f]*

2
frontends/ast/genrtlil.cc
View File

@ -554,6 +554,8 @@ struct AST_INTERNAL::ProcessGenerator
break;
default:
// ast->dumpAst(NULL, "ast> ");
// current_ast_mod->dumpAst(NULL, "mod> ");
log_abort();
}
}

3
frontends/ast/simplify.cc
View File

@ -401,6 +401,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_ALWAYS || type == AST_INITIAL)
{
if (current_always != nullptr)
log_error("Invalid nesting of always blocks and/or initializations at %s:%d.\n", filename.c_str(), linenum);
current_always = this;
current_always_clocked = false;

2
techlibs/ice40/synth_ice40.cc
View File

@ -70,7 +70,7 @@ struct SynthIce40Pass : public ScriptPass
log("\n");
log(" -vpr\n");
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this fueature is experimental and incomplete)\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");