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Merge pull request #21 from hansiglaser/master 

beautified write_intersynth, enabled multiple "-map" for the extract pass
This commit is contained in:
Clifford Wolf 2014-01-25 17:28:17 -08:00
parent c1ed2607fb e9a2094774
commit fd6ca84f3c
2 changed files with 33 additions and 16 deletions
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9
backends/intersynth/intersynth.cc
View File

@ -149,8 +149,10 @@ struct IntersynthBackend : public Backend {
log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n"); log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
std::set<std::string> constcells_code; std::set<std::string> constcells_code;
netlists_code += stringf("# Netlist of module %s\n", RTLIL::id2cstr(module->name));
netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name)); netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
// Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
for (auto wire_it : module->wires) { for (auto wire_it : module->wires) {
RTLIL::Wire *wire = wire_it.second; RTLIL::Wire *wire = wire_it.second;
if (wire->port_input || wire->port_output) { if (wire->port_input || wire->port_output) {
@ -162,6 +164,7 @@ struct IntersynthBackend : public Backend {
} }
} }
// Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
for (auto cell_it : module->cells) for (auto cell_it : module->cells)
{ {
RTLIL::Cell *cell = cell_it.second; RTLIL::Cell *cell = cell_it.second;
@ -194,16 +197,22 @@ struct IntersynthBackend : public Backend {
netlists_code += node_code + "\n"; netlists_code += node_code + "\n";
} }
if (constcells_code.size() > 0)
netlists_code += "# constant cells\n";
for (auto code : constcells_code) for (auto code : constcells_code)
netlists_code += code; netlists_code += code;
netlists_code += "\n";
} }
if (!flag_notypes) { if (!flag_notypes) {
fprintf(f, "### Connection Types\n");
for (auto code : conntypes_code) for (auto code : conntypes_code)
fprintf(f, "%s", code.c_str()); fprintf(f, "%s", code.c_str());
fprintf(f, "\n### Cell Types\n");
for (auto code : celltypes_code) for (auto code : celltypes_code)
fprintf(f, "%s", code.c_str()); fprintf(f, "%s", code.c_str());
} }
fprintf(f, "\n### Netlists\n");
fprintf(f, "%s", netlists_code.c_str()); fprintf(f, "%s", netlists_code.c_str());
for (auto lib : libs) for (auto lib : libs)

40
passes/extract/extract.cc
View File

@ -312,7 +312,8 @@ struct ExtractPass : public Pass {
log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n"); log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n");
log("\n"); log("\n");
log(" -map <map_file>\n"); log(" -map <map_file>\n");
log(" use the modules in this file as reference\n"); log(" use the modules in this file as reference. This option can be used\n");
log(" multiple times.\n");
log("\n"); log("\n");
log(" -verbose\n"); log(" -verbose\n");
log(" print debug output while analyzing\n"); log(" print debug output while analyzing\n");
@ -384,7 +385,8 @@ struct ExtractPass : public Pass {
SubCircuitSolver solver; SubCircuitSolver solver;
std::string filename; std::vector<std::string> map_filenames;
std::string mine_outfile;
bool constports = false; bool constports = false;
bool nodefaultswaps = false; bool nodefaultswaps = false;
@ -399,11 +401,15 @@ struct ExtractPass : public Pass {
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-map" && argidx+1 < args.size()) { if (args[argidx] == "-map" && argidx+1 < args.size()) {
filename = args[++argidx]; if (mine_mode)
log_cmd_error("You cannot mix -map and -mine.\n");
map_filenames.push_back(args[++argidx]);
continue; continue;
} }
if (args[argidx] == "-mine" && argidx+1 < args.size()) { if (args[argidx] == "-mine" && argidx+1 < args.size()) {
filename = args[++argidx]; if (!map_filenames.empty())
log_cmd_error("You cannot mix -map and -mine.\n");
mine_outfile = args[++argidx];
mine_mode = true; mine_mode = true;
continue; continue;
} }
@ -510,23 +516,25 @@ struct ExtractPass : public Pass {
solver.addSwappablePorts("$_XOR_", "\\A", "\\B"); solver.addSwappablePorts("$_XOR_", "\\A", "\\B");
} }
if (filename.empty()) if (map_filenames.empty() && mine_outfile.empty())
log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n"); log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n");
RTLIL::Design *map = NULL; RTLIL::Design *map = NULL;
if (!mine_mode) if (!mine_mode)
{ {
FILE *f = fopen(filename.c_str(), "rt");
if (f == NULL)
log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
map = new RTLIL::Design; map = new RTLIL::Design;
Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); for (auto &filename : map_filenames) {
fclose(f); FILE *f = fopen(filename.c_str(), "rt");
if (f == NULL)
log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
fclose(f);
if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") { if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
Pass::call(map, "proc"); Pass::call(map, "proc");
Pass::call(map, "opt_clean"); Pass::call(map, "opt_clean");
}
} }
} }
@ -658,10 +666,10 @@ struct ExtractPass : public Pass {
} }
} }
FILE *f = fopen(filename.c_str(), "wt"); FILE *f = fopen(mine_outfile.c_str(), "wt");
if (f == NULL) if (f == NULL)
log_error("Can't open output file `%s'.\n", filename.c_str()); log_error("Can't open output file `%s'.\n", mine_outfile.c_str());
Backend::backend_call(map, f, filename, "ilang"); Backend::backend_call(map, f, mine_outfile, "ilang");
fclose(f); fclose(f);
} }