Merge remote-tracking branch 'origin/master' into xc7dsp

Makefile

@@ -115,7 +115,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.9+406
+YOSYS_VER := 0.9+431
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 

backends/aiger/aiger.cc

@@ -101,7 +101,7 @@ struct AigerWriter
 		return a;
 	}
 
-	AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
+	AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
@@ -367,6 +367,12 @@ struct AigerWriter
 				aig_latchin.push_back(a);
 		}
 
+		if (lmode && aig_l == 0) {
+			aig_m++, aig_l++;
+			aig_latchinit.push_back(0);
+			aig_latchin.push_back(0);
+		}
+
 		if (!initstate_bits.empty() || !init_inputs.empty())
 			aig_latchin.push_back(1);
 
@@ -704,9 +710,9 @@ struct AigerBackend : public Backend {
 		log("    -vmap <filename>\n");
 		log("        like -map, but more verbose\n");
 		log("\n");
-		log("    -I, -O, -B\n");
+		log("    -I, -O, -B, -L\n");
-		log("        If the design contains no input/output/assert then create one\n");
+		log("        If the design contains no input/output/assert/flip-flop then create one\n");
-		log("        dummy input/output/bad_state pin to make the tools reading the\n");
+		log("        dummy input/output/bad_state-pin or latch to make the tools reading the\n");
 		log("        AIGER file happy.\n");
 		log("\n");
 	}
@@ -720,6 +726,7 @@ struct AigerBackend : public Backend {
 		bool imode = false;
 		bool omode = false;
 		bool bmode = false;
+		bool lmode = false;
 		std::string map_filename;
 
 		log_header(design, "Executing AIGER backend.\n");
@@ -764,6 +771,10 @@ struct AigerBackend : public Backend {
 				bmode = true;
 				continue;
 			}
+			if (args[argidx] == "-L") {
+				lmode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);
@@ -773,7 +784,7 @@ struct AigerBackend : public Backend {
 		if (top_module == nullptr)
 			log_error("Can't find top module in current design!\n");
 
-		AigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
+		AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode);
 		writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
 
 		if (!map_filename.empty()) {

backends/btor/btor.cc

@@ -685,7 +685,7 @@ struct BtorWorker
 				}
 				else
 				{
-					int nid_init_val = next_nid++;
+					nid_init_val = next_nid++;
 					btorf("%d state %d\n", nid_init_val, sid);
 
 					for (int i = 0; i < nwords; i++) {

frontends/ast/simplify.cc

@@ -2895,8 +2895,15 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
 void AstNode::expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map)
 {
 	if (!index_var.empty() && type == AST_IDENTIFIER && str == index_var) {
+		if (children.empty()) {
 			current_scope[index_var]->children[0]->cloneInto(this);
-		return;
+		} else {
+			AstNode *p = new AstNode(AST_LOCALPARAM, current_scope[index_var]->children[0]->clone());
+			p->str = stringf("$genval$%d", autoidx++);
+			current_ast_mod->children.push_back(p);
+			str = p->str;
+			id2ast = p;
+		}
 	}
 
 	if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0)

frontends/verilog/const2ast.cc

@@ -85,10 +85,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 			digits.push_back(10 + *str - 'A');
 		else if (*str == 'x' || *str == 'X')
 			digits.push_back(0xf0);
-		else if (*str == 'z' || *str == 'Z')
+		else if (*str == 'z' || *str == 'Z' || *str == '?')
 			digits.push_back(0xf1);
-		else if (*str == '?')
-			digits.push_back(0xf2);
 		str++;
 	}
 
@@ -112,8 +110,6 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 					data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx);
 				else if (*it == 0xf1)
 					data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz);
-				else if (*it == 0xf2)
-					data.push_back(RTLIL::Sa);
 				else
 					data.push_back((*it & bitmask) ? State::S1 : State::S0);
 			}
@@ -199,13 +195,13 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
 	if (str == endptr)
 		len_in_bits = -1;
 
-	// The "<bits>'s?[bodhBODH]<digits>" syntax
+	// The "<bits>'[sS]?[bodhBODH]<digits>" syntax
 	if (*endptr == '\'')
 	{
 		std::vector<RTLIL::State> data;
 		bool is_signed = false;
 		bool is_unsized = len_in_bits < 0;
-		if (*(endptr+1) == 's') {
+		if (*(endptr+1) == 's' || *(endptr+1) == 'S') {
 			is_signed = true;
 			endptr++;
 		}

frontends/verilog/verilog_lexer.l

@@ -239,7 +239,7 @@ YOSYS_NAMESPACE_END
 	return TOK_CONSTVAL;
 }
 
-[0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
+[0-9]*[ \t]*\'[sS]?[bodhBODH]?[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
 	frontend_verilog_yylval.string = new std::string(yytext);
 	return TOK_CONSTVAL;
 }

kernel/sigtools.h

@@ -135,9 +135,11 @@ struct SigPool
 	}
 };
 
-template <typename T, class Compare = std::less<T>>
+template <typename T, class Compare = void>
 struct SigSet
 {
+	static_assert(!std::is_same<Compare,void>::value, "Default value for `Compare' class not found for SigSet<T>. Please specify.");
+
 	struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
 		bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
 		bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
@@ -220,6 +222,13 @@ struct SigSet
 	}
 };
 
+template<typename T>
+class SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};
+template<typename T>
+using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;
+template<typename T>
+class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
+
 struct SigMap
 {
 	mfp<SigBit> database;

passes/opt/opt_expr.cc

@@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 
 			if (b.is_fully_const()) {
+				if (b.is_fully_undef()) {
+					RTLIL::SigSpec input = b;
+					ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y))));
+				} else
 				if (b.as_bool() == (cell->type == ID($eq))) {
 					RTLIL::SigSpec input = b;
 					ACTION_DO(ID::Y, cell->getPort(ID::A));

passes/techmap/alumacc.cc

@@ -48,14 +48,25 @@ struct AlumaccWorker
 		RTLIL::SigSpec cached_cf, cached_of, cached_sf;
 
 		RTLIL::SigSpec get_lt() {
-			if (GetSize(cached_lt) == 0)
+			if (GetSize(cached_lt) == 0) {
-				cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
+				if (is_signed) {
+					get_of();
+					get_sf();
+					cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
+				}
+				else
+					cached_lt = get_cf();
+			}
 			return cached_lt;
 		}
 
 		RTLIL::SigSpec get_gt() {
-			if (GetSize(cached_gt) == 0)
+			if (GetSize(cached_gt) == 0) {
-				cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
+				get_lt();
+				get_eq();
+				SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
+				cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
+			}
 			return cached_gt;
 		}
 

techlibs/anlogic/cells_sim.v

@@ -1,5 +1,5 @@
 module AL_MAP_SEQ (
-	output q,
+	output reg q,
 	input ce,
 	input clk,
 	input sr,
@@ -9,6 +9,71 @@ module AL_MAP_SEQ (
 	parameter REGSET = "RESET"; //RESET/SET
 	parameter SRMUX = "SR"; //SR/INV
 	parameter SRMODE = "SYNC"; //SYNC/ASYNC
+
+	wire clk_ce;
+	assign clk_ce = ce ? clk : 1'b0;
+
+	wire srmux;
+	generate
+		case (SRMUX)
+			"SR": assign srmux = sr;
+			"INV": assign srmux = ~sr;
+			default: assign srmux = sr;
+		endcase
+	endgenerate	
+
+	wire regset;
+	generate
+		case (REGSET)
+			"RESET": assign regset = 1'b0;
+			"SET": assign regset = 1'b1;
+			default: assign regset = 1'b0;
+		endcase
+	endgenerate
+
+	initial q = regset;
+
+	generate
+   		if (DFFMODE == "FF") 
+		begin
+			if (SRMODE == "ASYNC") 
+			begin
+				always @(posedge clk_ce, posedge srmux)
+					if (srmux)
+						q <= regset;
+					else 
+						q <= d;	
+			end 
+			else
+			begin
+				always @(posedge clk_ce)
+					if (srmux)
+						q <= regset;
+					else 
+						q <= d;	
+			end
+		end
+		else
+		begin
+			// DFFMODE == "LATCH"
+			if (SRMODE == "ASYNC") 
+			begin
+				always @(clk_ce, srmux)
+					if (srmux)
+						q <= regset;
+					else 
+						q <= d;	
+			end 
+			else
+			begin
+				always @(clk_ce)
+					if (srmux)
+						q <= regset;
+					else 
+						q <= d;	
+			end
+		end
+    endgenerate
 endmodule
 
 module AL_MAP_LUT1 (
@@ -17,7 +82,8 @@ module AL_MAP_LUT1 (
 );
 	parameter [1:0] INIT = 2'h0;
 	parameter EQN = "(A)";
-	assign o = INIT >> a;
+
+	assign o = a ? INIT[1] : INIT[0];	
 endmodule
 
 module AL_MAP_LUT2 (
@@ -27,7 +93,9 @@ module AL_MAP_LUT2 (
 );
 	parameter [3:0] INIT = 4'h0;
 	parameter EQN = "(A)";
-	assign o = INIT >> {b, a};
+
+	wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
+	assign o = a ? s1[1] : s1[0];	
 endmodule
 
 module AL_MAP_LUT3 (
@@ -38,7 +106,10 @@ module AL_MAP_LUT3 (
 );
 	parameter [7:0] INIT = 8'h0;
 	parameter EQN = "(A)";
-	assign o = INIT >> {c, b, a};
+
+	wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
+	wire [1:0] s1 = b ?   s2[ 3:2] :   s2[1:0];
+	assign o = a ? s1[1] : s1[0];	
 endmodule
 
 module AL_MAP_LUT4 (
@@ -50,7 +121,11 @@ module AL_MAP_LUT4 (
 );
 	parameter [15:0] INIT = 16'h0;
 	parameter EQN = "(A)";
-	assign o = INIT >> {d, c, b, a};
+
+	wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
+	wire [3:0] s2 = c ?   s3[ 7:4] :   s3[3:0];
+	wire [1:0] s1 = b ?   s2[ 3:2] :   s2[1:0];
+	assign o = a ? s1[1] : s1[0];	
 endmodule
 
 module AL_MAP_LUT5 (
@@ -100,4 +175,18 @@ module AL_MAP_ADDER (
   output [1:0] o
 );
 	parameter ALUTYPE = "ADD";
+
+	generate
+		case (ALUTYPE)
+			"ADD": 		 assign o = a + b + c;
+			"SUB": 		 assign o = a - b - c;
+			"A_LE_B":    assign o = a - b - c;
+
+			"ADD_CARRY":    assign o = {  a, 1'b0 };
+			"SUB_CARRY":    assign o = { ~a, 1'b0 };
+			"A_LE_B_CARRY": assign o = {  a, 1'b0 };
+			default: assign o = a + b + c;
+		endcase
+	endgenerate	
+
 endmodule

techlibs/efinix/cells_sim.v

@@ -6,6 +6,11 @@ module EFX_LUT4(
    input I3
 );
 	parameter LUTMASK = 16'h0000;
+
+	wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
+	wire [3:0] s2 = I2 ?      s3[ 7:4] :      s3[3:0];
+	wire [1:0] s1 = I1 ?      s2[ 3:2] :      s2[1:0];
+	assign O = I0 ? s1[1] : s1[0];	   
 endmodule
 
 module EFX_ADD(
@@ -17,10 +22,18 @@ module EFX_ADD(
 );
    parameter I0_POLARITY   = 1;
    parameter I1_POLARITY   = 1;
+
+   wire i0;
+   wire i1;
+
+   assign i0 = I0_POLARITY ? I0 : ~I0;
+   assign i1 = I1_POLARITY ? I1 : ~I1;
+
+   assign {CO, O} = i0 + i1 + CI;
 endmodule
 
 module EFX_FF(
-   output Q,
+   output reg Q,
    input D,
    input CE,
    input CLK,
@@ -33,6 +46,53 @@ module EFX_FF(
    parameter SR_VALUE = 0;
    parameter SR_SYNC_PRIORITY = 0;
    parameter D_POLARITY = 1;
+
+   wire clk;
+   wire ce;
+   wire sr;
+   wire d;
+   wire prio;
+   wire sync;
+   wire async;
+
+   assign clk = CLK_POLARITY ? CLK : ~CLK;
+   assign ce = CE_POLARITY ? CE : ~CE;
+   assign sr = SR_POLARITY ? SR : ~SR;
+   assign d = D_POLARITY ? D : ~D;
+  
+   generate
+   	if (SR_SYNC == 1) 
+      begin
+         if (SR_SYNC_PRIORITY == 1) 
+         begin
+            always @(posedge clk)
+               if (sr)
+                  Q <= SR_VALUE;
+               else if (ce)
+                  Q <= d;
+         end
+         else
+         begin
+            always @(posedge clk)
+               if (ce)
+               begin
+                  if (sr)
+                     Q <= SR_VALUE;
+                  else
+                     Q <= d;
+               end
+         end
+      end
+      else
+      begin
+         always @(posedge clk or posedge sr)
+            if (sr)
+               Q <= SR_VALUE;
+            else if (ce)
+               Q <= d;
+         
+      end
+   endgenerate
 endmodule
 
 module EFX_GBUFCE(
@@ -41,6 +101,12 @@ module EFX_GBUFCE(
    output O
 );
    parameter CE_POLARITY = 1'b1;
+
+   wire ce;
+   assign ce = CE_POLARITY ? CE : ~CE;
+   
+   assign O = I & ce;
+   
 endmodule
 
 module EFX_RAM_5K(

techlibs/xilinx/Makefile.inc

@@ -25,7 +25,10 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
 
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_cells_xtra.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6v_cells_xtra.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_cells_xtra.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))

techlibs/xilinx/cells_xtra.py

@@ -14,9 +14,258 @@ class Cell:
         self.port_attrs = port_attrs
 
 
-CELLS = [
+XC6S_CELLS = [
-    # Design elements types listed in Xilinx UG953
+    # Design elements types listed in Xilinx UG615.
-    Cell('BSCANE2', keep=True),
+
+    # Advanced.
+    Cell('MCB'),
+    Cell('PCIE_A1'),
+
+    # Arithmetic functions.
+    Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}),
+
+    # Clock components.
+    # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
+    Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
+    Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
+    Cell('DCM_CLKGEN'),
+    Cell('DCM_SP'),
+    Cell('PLL_BASE'),
+
+    # Config/BSCAN components.
+    Cell('BSCAN_SPARTAN6', keep=True),
+    Cell('DNA_PORT'),
+    Cell('ICAP_SPARTAN6', keep=True),
+    Cell('POST_CRC_INTERNAL'),
+    Cell('STARTUP_SPARTAN6', keep=True),
+    Cell('SUSPEND_SYNC', keep=True),
+
+    # I/O components.
+    Cell('GTPA1_DUAL'),
+    # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
+    Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
+    Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
+    Cell('ISERDES2', port_attrs={
+        'CLK0': ['clkbuf_sink'],
+        'CLK1': ['clkbuf_sink'],
+        'CLKDIV': ['clkbuf_sink'],
+    }),
+    Cell('KEEPER'),
+    # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OSERDES2', port_attrs={
+        'CLK0': ['clkbuf_sink'],
+        'CLK1': ['clkbuf_sink'],
+        'CLKDIV': ['clkbuf_sink'],
+    }),
+    Cell('PULLDOWN'),
+    Cell('PULLUP'),
+
+    # RAM/ROM.
+    #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # NOTE: not in the official library guide!
+    Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # NOTE: not in the official library guide!
+    Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAMB8BWER', port_attrs={'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}),
+    # Cell('RAMB16BWER', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
+    Cell('ROM128X1'),
+    Cell('ROM256X1'),
+    Cell('ROM32X1'),
+    Cell('ROM64X1'),
+
+    # Registers/latches.
+    # Cell('FDCE'),
+    # Cell('FDPE'),
+    # Cell('FDRE'),
+    # Cell('FDSE'),
+    Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
+    Cell('LDCE'),
+    Cell('LDPE'),
+    Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
+
+    # Slice/CLB primitives.
+    # Cell('CARRY4'),
+    Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('LUT1'),
+    # Cell('LUT2'),
+    # Cell('LUT3'),
+    # Cell('LUT4'),
+    # Cell('LUT5'),
+    # Cell('LUT6'),
+    # Cell('LUT6_2'),
+    # Cell('MUXF7'),
+    # Cell('MUXF8'),
+    # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+]
+
+
+XC6V_CELLS = [
+    # Design elements types listed in Xilinx UG623.
+
+    # Advanced.
+    Cell('PCIE_2_0'),
+    Cell('SYSMON'),
+
+    # Arithmetic functions.
+    Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+
+    # Clock components.
+    # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+    #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
+    #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('MMCM_ADV'),
+    Cell('MMCM_BASE'),
+
+    # Config/BSCAN components.
+    Cell('BSCAN_VIRTEX6', keep=True),
+    Cell('CAPTURE_VIRTEX6', keep=True),
+    Cell('DNA_PORT'),
+    Cell('EFUSE_USR'),
+    Cell('FRAME_ECC_VIRTEX6'),
+    Cell('ICAP_VIRTEX6', keep=True),
+    Cell('STARTUP_VIRTEX6', keep=True),
+    Cell('USR_ACCESS_VIRTEX6'),
+
+    # I/O components.
+    Cell('DCIRESET', keep=True),
+    Cell('GTHE1_QUAD'),
+    Cell('GTXE1'),
+    # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
+    Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('ISERDESE1', port_attrs={
+        'CLK': ['clkbuf_sink'],
+        'CLKB': ['clkbuf_sink'],
+        'OCLK': ['clkbuf_sink'],
+        'CLKDIV': ['clkbuf_sink'],
+    }),
+    Cell('KEEPER'),
+    # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
+    Cell('PULLDOWN'),
+    Cell('PULLUP'),
+    Cell('TEMAC_SINGLE'),
+
+    # RAM/ROM.
+    Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # NOTE: not in the official library guide!
+    Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+    # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+    Cell('ROM128X1'),
+    Cell('ROM256X1'),
+    Cell('ROM32X1'),
+    Cell('ROM64X1'),
+
+    # Registers/latches.
+    # Cell('FDCE'),
+    # Cell('FDPE'),
+    # Cell('FDRE'),
+    # Cell('FDSE'),
+    Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
+    Cell('LDCE'),
+    Cell('LDPE'),
+    Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
+
+    # Slice/CLB primitives.
+    # Cell('CARRY4'),
+    Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('LUT1'),
+    # Cell('LUT2'),
+    # Cell('LUT3'),
+    # Cell('LUT4'),
+    # Cell('LUT5'),
+    # Cell('LUT6'),
+    # Cell('LUT6_2'),
+    # Cell('MUXF7'),
+    # Cell('MUXF8'),
+    # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+]
+
+
+XC7_CELLS = [
+    # Design elements types listed in Xilinx UG953.
+
+    # Advanced.
+    Cell('GTHE2_CHANNEL'),
+    Cell('GTHE2_COMMON'),
+    Cell('GTPE2_CHANNEL'),
+    Cell('GTPE2_COMMON'),
+    Cell('GTXE2_CHANNEL'),
+    Cell('GTXE2_COMMON'),
+    Cell('PCIE_2_1'),
+    Cell('PCIE_3_0'),
+    Cell('XADC'),
+
+    # Arithmetic functions.
+    Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+
+    # Clock components.
     # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
     Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
     Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
@@ -30,26 +279,23 @@ CELLS = [
     Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
     Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
     Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('MMCME2_ADV'),
+    Cell('MMCME2_BASE'),
+    Cell('PLLE2_ADV'),
+    Cell('PLLE2_BASE'),
+
+    # Config/BSCAN components.
+    Cell('BSCANE2', keep=True),
     Cell('CAPTUREE2', keep=True),
-    # Cell('CARRY4'),
-    Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
-    Cell('DCIRESET', keep=True),
     Cell('DNA_PORT'),
-    Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
     Cell('EFUSE_USR'),
-    # Cell('FDCE'),
-    # Cell('FDPE'),
-    # Cell('FDRE'),
-    # Cell('FDSE'),
-    Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
-    Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
     Cell('FRAME_ECCE2'),
-    Cell('GTHE2_CHANNEL'),
+    Cell('ICAPE2', keep=True),
-    Cell('GTHE2_COMMON'),
+    Cell('STARTUPE2', keep=True),
-    Cell('GTPE2_CHANNEL'),
+    Cell('USR_ACCESSE2'),
-    Cell('GTPE2_COMMON'),
+
-    Cell('GTXE2_CHANNEL'),
+    # I/O components.
-    Cell('GTXE2_COMMON'),
+    Cell('DCIRESET', keep=True),
     # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
     Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
     Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
@@ -63,9 +309,6 @@ CELLS = [
     Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
     Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
     Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
-    Cell('ICAPE2', keep=True),
-    Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
-    Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
     Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
     Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
     Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
@@ -77,6 +320,7 @@ CELLS = [
     Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
     Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
     Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
     Cell('ISERDESE2', port_attrs={
         'CLK': ['clkbuf_sink'],
         'CLKB': ['clkbuf_sink'],
@@ -86,24 +330,10 @@ CELLS = [
         'CLKDIVP': ['clkbuf_sink'],
     }),
     Cell('KEEPER'),
-    Cell('LDCE'),
-    Cell('LDPE'),
-    # Cell('LUT1'),
-    # Cell('LUT2'),
-    # Cell('LUT3'),
-    # Cell('LUT4'),
-    # Cell('LUT5'),
-    # Cell('LUT6'),
-    #Cell('LUT6_2'),
-    Cell('MMCME2_ADV'),
-    Cell('MMCME2_BASE'),
-    # Cell('MUXF7'),
-    # Cell('MUXF8'),
     # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
     Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
     Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
     Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
-    Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
     Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
     Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
     Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
@@ -113,11 +343,12 @@ CELLS = [
     Cell('PHASER_OUT_PHY'),
     Cell('PHASER_REF'),
     Cell('PHY_CONTROL'),
-    Cell('PLLE2_ADV'),
-    Cell('PLLE2_BASE'),
-    Cell('PS7', keep=True),
     Cell('PULLDOWN'),
     Cell('PULLUP'),
+
+    # RAM/ROM.
+    Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
     #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
     Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
     Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
@@ -130,6 +361,7 @@ CELLS = [
     #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
     Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
     Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # NOTE: not in the official library guide!
     Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
     # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
     # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
@@ -137,13 +369,207 @@ CELLS = [
     Cell('ROM256X1'),
     Cell('ROM32X1'),
     Cell('ROM64X1'),
-    #Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+
-    #Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Registers/latches.
-    Cell('STARTUPE2', keep=True),
+    # Cell('FDCE'),
-    Cell('USR_ACCESSE2'),
+    # Cell('FDPE'),
-    Cell('XADC'),
+    # Cell('FDRE'),
+    # Cell('FDSE'),
+    Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
+    Cell('LDCE'),
+    Cell('LDPE'),
+    Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
+
+    # Slice/CLB primitives.
+    # Cell('CARRY4'),
+    Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('LUT1'),
+    # Cell('LUT2'),
+    # Cell('LUT3'),
+    # Cell('LUT4'),
+    # Cell('LUT5'),
+    # Cell('LUT6'),
+    # Cell('LUT6_2'),
+    # Cell('MUXF7'),
+    # Cell('MUXF8'),
+    # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+
+    # NOTE: not in the official library guide!
+    Cell('PS7', keep=True),
 ]
 
+
+XCU_CELLS = [
+    # Design elements types listed in Xilinx UG974.
+
+    # Advanced.
+    Cell('CMAC'),
+    Cell('CMACE4'),
+    Cell('GTHE3_CHANNEL'),
+    Cell('GTHE3_COMMON'),
+    Cell('GTHE4_CHANNEL'),
+    Cell('GTHE4_COMMON'),
+    Cell('GTYE3_CHANNEL'),
+    Cell('GTYE3_COMMON'),
+    Cell('GTYE4_CHANNEL'),
+    Cell('GTYE4_COMMON'),
+    Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('ILKN'),
+    Cell('ILKNE4'),
+    Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('PCIE40E4'),
+    Cell('PCIE_3_1'),
+    Cell('SYSMONE1'),
+    Cell('SYSMONE4'),
+
+    # Arithmetic functions.
+    Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}),
+
+    # Blockram.
+    Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+    Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+    Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
+
+    # CLB.
+    # Cell('LUT6_2'),
+    #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('AND2B1L'),
+    Cell('CARRY8'),
+    Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('LUT1'),
+    # Cell('LUT2'),
+    # Cell('LUT3'),
+    # Cell('LUT4'),
+    # Cell('LUT5'),
+    # Cell('LUT6'),
+    # Cell('MUXF7'),
+    # Cell('MUXF8'),
+    Cell('MUXF9'),
+    Cell('OR2L'),
+    # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+
+    # Clock.
+    # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFG_GT_SYNC'),
+    Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}),
+    #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('MMCME3_ADV'),
+    Cell('MMCME3_BASE'),
+    Cell('MMCME4_ADV'),
+    Cell('MMCME4_BASE'),
+    Cell('PLLE3_ADV'),
+    Cell('PLLE3_BASE'),
+    Cell('PLLE4_ADV'),
+    Cell('PLLE4_BASE'),
+
+    # Configuration.
+    Cell('BSCANE2', keep=True),
+    Cell('DNA_PORTE2'),
+    Cell('EFUSE_USR'),
+    Cell('FRAME_ECCE3'),
+    Cell('ICAPE3', keep=True),
+    Cell('MASTER_JTAG', keep=True),
+    Cell('STARTUPE3', keep=True),
+    Cell('USR_ACCESSE2'),
+
+    # I/O.
+    Cell('BITSLICE_CONTROL', keep=True),
+    Cell('DCIRESET', keep=True),
+    Cell('HPIO_VREF'),
+    # XXX
+    # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDSE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
+    Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('ISERDESE3', port_attrs={
+        'CLK': ['clkbuf_sink'],
+        'CLK_B': ['clkbuf_sink'],
+        'FIFO_RD_CLK': ['clkbuf_sink'],
+        'CLKDIV': ['clkbuf_sink'],
+    }),
+    Cell('KEEPER'),
+    # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
+    Cell('PULLDOWN'),
+    Cell('PULLUP'),
+    Cell('RIU_OR'),
+    Cell('RX_BITSLICE'),
+    Cell('RXTX_BITSLICE'),
+    Cell('TX_BITSLICE'),
+    Cell('TX_BITSLICE_TRI'),
+
+    # Registers.
+    # Cell('FDCE'),
+    # Cell('FDPE'),
+    # Cell('FDRE'),
+    # Cell('FDSE'),
+    Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
+    Cell('LDCE'),
+    Cell('LDPE'),
+    Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
+
+    # NOTE: not in the official library guide!
+    Cell('PS8', keep=True),
+]
+
+
 class State(Enum):
     OUTSIDE = auto()
     IN_MODULE = auto()
@@ -235,23 +661,31 @@ def xtract_cell_decl(cell, dirs, outf):
     sys.exit(1)
 
 if __name__ == '__main__':
-    parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from Vivado.')
+    parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from ISE and Vivado.')
     parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
+    parser.add_argument('ise_dir', nargs='?', default='/opt/Xilinx/ISE/14.7')
     args = parser.parse_args()
 
     dirs = [
         os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
         os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
+        os.path.join(args.ise_dir, 'ISE_DS/ISE/verilog/xeclib/unisims'),
     ]
     for dir in dirs:
         if not os.path.isdir(dir):
             print('{} is not a directory'.format(dir))
 
+    for ofile, cells in [
+        ('xc6s_cells_xtra.v', XC6S_CELLS),
+        ('xc6v_cells_xtra.v', XC6V_CELLS),
+        ('xc7_cells_xtra.v', XC7_CELLS),
+        ('xcu_cells_xtra.v', XCU_CELLS),
+    ]:
         out = StringIO()
-    for cell in CELLS:
+        for cell in cells:
             xtract_cell_decl(cell, dirs, out)
 
-    with open('cells_xtra.v', 'w') as f:
+        with open(ofile, 'w') as f:
             f.write('// Created by cells_xtra.py from Xilinx models\n')
             f.write('\n')
             f.write(out.getvalue())

techlibs/xilinx/synth_xilinx.cc

@@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
-		log("    -family {xcup|xcu|xc7|xc6s}\n");
+		log("    -family {xcup|xcu|xc7|xc6v|xc6s}\n");
 		log("        run synthesis for the specified Xilinx architecture\n");
 		log("        generate the synthesis netlist for the specified family.\n");
 		log("        default: xc7\n");
@@ -252,7 +252,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 		extra_args(args, argidx, design);
 
-		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
+		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" & family != "xc6s")
 			log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
 
 		if (widemux != 0 && widemux < 2)
@@ -276,7 +276,7 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		std::string ff_map_file;
 		if (help_mode)
-			ff_map_file = "+/xilinx/xc6s_ff_map.v";
+			ff_map_file = "+/xilinx/{family}_ff_map.v";
 		else if (family == "xc6s")
 			ff_map_file = "+/xilinx/xc6s_ff_map.v";
 		else
@@ -288,13 +288,22 @@ struct SynthXilinxPass : public ScriptPass
 			else
 				run("read_verilog -lib +/xilinx/cells_sim.v");
 
-			run("read_verilog -lib +/xilinx/cells_xtra.v");
+			if (help_mode)
+				run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
+			else if (family == "xc6s")
+				run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v");
+			else if (family == "xc6v")
+				run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v");
+			else if (family == "xc7")
+				run("read_verilog -lib +/xilinx/xc7_cells_xtra.v");
+			else if (family == "xcu" || family == "xcup")
+				run("read_verilog -lib +/xilinx/xcu_cells_xtra.v");
 
 			if (help_mode) {
 				run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
 			} else if (family == "xc6s") {
 				run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
-			} else if (family == "xc7") {
+			} else if (family == "xc6v" || family == "xc7") {
 				run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
 			}
 
@@ -357,7 +366,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family == "xc6s") {
 					run("memory_bram -rules +/xilinx/xc6s_brams.txt");
 					run("techmap -map +/xilinx/xc6s_brams_map.v");
-				} else if (family == "xc7") {
+				} else if (family == "xc6v" || family == "xc7") {
 					run("memory_bram -rules +/xilinx/xc7_brams.txt");
 					run("techmap -map +/xilinx/xc7_brams_map.v");
 				} else {