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fix indentation across files

This commit is contained in:
Stefan Biereigel 2019-05-23 13:42:30 +02:00
parent 075a48d3fa
commit fd003e0e97
4 changed files with 80 additions and 60 deletions
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2
frontends/ast/ast.cc
View File

@ -195,6 +195,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
is_logic = false; is_logic = false;
is_signed = false; is_signed = false;
is_string = false; is_string = false;
is_wand = false;
is_wor = false;
was_checked = false; was_checked = false;
range_valid = false; range_valid = false;
range_swapped = false; range_swapped = false;

28
frontends/ast/genrtlil.cc
View File

@ -961,7 +961,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n"); log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n");
wandwor2rtlil(this, wire); wandwor2rtlil(this, wire);
} }
} }
break; break;
@ -1508,7 +1507,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::Cell *reduce_cell = iter->second; RTLIL::Cell *reduce_cell = iter->second;
RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A"); RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A");
int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int(); int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int();
log_warning("%d\n", reduce_cell_in.size());
RTLIL::Wire *new_reduce_input = current_module->addWire( RTLIL::Wire *new_reduce_input = current_module->addWire(
stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width)); stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width));
@ -1576,14 +1574,34 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
if (child->type == AST_ARGUMENT) { if (child->type == AST_ARGUMENT) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (child->children.size() > 0) RTLIL::SigSpec new_sig;
if (child->children.size() > 0) {
sig = child->children[0]->genRTLIL(); sig = child->children[0]->genRTLIL();
for (int i = 0; i < GetSize(sig); i++) {
std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(sig[i].wire);
if (iter == wire_logic_map.end()) {
new_sig.append(sig[i]);
} else {
RTLIL::Cell *reduce_cell = iter->second;
RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A");
int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int();
RTLIL::Wire *new_reduce_input = current_module->addWire(
stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width));
new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
reduce_cell_in.append(new_reduce_input);
reduce_cell->setPort("\\A", reduce_cell_in);
reduce_cell->fixup_parameters();
new_sig.append(new_reduce_input);
}
}
}
if (child->str.size() == 0) { if (child->str.size() == 0) {
char buf[100]; char buf[100];
snprintf(buf, 100, "$%d", ++port_counter); snprintf(buf, 100, "$%d", ++port_counter);
cell->setPort(buf, sig); cell->setPort(buf, new_sig);
} else { } else {
cell->setPort(child->str, sig); cell->setPort(child->str, new_sig);
} }
continue; continue;
} }